diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long/se/40.perlbmk | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long/se/40.perlbmk')
4 files changed, 1688 insertions, 1670 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index bd567cfd0..ca0137184 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.652381 # Number of seconds simulated -sim_ticks 652381344000 # Number of ticks simulated -final_tick 652381344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.643360 # Number of seconds simulated +sim_ticks 643359514000 # Number of ticks simulated +final_tick 643359514000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170851 # Simulator instruction rate (inst/s) -host_op_rate 170851 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61139648 # Simulator tick rate (ticks/s) -host_mem_usage 240236 # Number of bytes of host memory used -host_seconds 10670.35 # Real time elapsed on the host +host_inst_rate 181804 # Simulator instruction rate (inst/s) +host_op_rate 181804 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64159253 # Simulator tick rate (ticks/s) +host_mem_usage 240484 # Number of bytes of host memory used +host_seconds 10027.54 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 191616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94459904 # Number of bytes read from this memory -system.physmem.bytes_read::total 94651520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 191616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 191616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory -system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1475936 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1478930 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 293718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 144792467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 145086184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 293718 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 293718 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6562836 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6562836 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6562836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 293718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 144792467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 151649021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1478931 # Total number of read requests seen -system.physmem.writeReqs 66898 # Total number of write requests seen -system.physmem.cpureqs 1545829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 94651520 # Total number of bytes read from memory -system.physmem.bytesWritten 4281472 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 94651520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4281472 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3904 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 179328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30296192 # Number of bytes read from this memory +system.physmem.bytes_read::total 30475520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473378 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476180 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 278737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47090610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47369347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 278737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 278737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6655862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6655862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6655862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 278737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47090610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54025209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476180 # Total number of read requests seen +system.physmem.writeReqs 66908 # Total number of write requests seen +system.physmem.cpureqs 543088 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30475520 # Total number of bytes read from memory +system.physmem.bytesWritten 4282112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 30475520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 91678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 92672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 91873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 92907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 92232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 92052 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 92519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 92192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 92430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 91951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 91930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 92149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 91869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 92596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 91765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 92212 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29588 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29989 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29833 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29824 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29667 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29798 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4346 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4345 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4311 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 4159 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 4199 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 4202 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4170 # Tr system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 652381327000 # Total gap between requests +system.physmem.totGap 643359452500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1478931 # Categorize read packet sizes +system.physmem.readPktSize::6 476180 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66898 # categorize write packet sizes +system.physmem.writePktSize::6 66908 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1404621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 406668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see @@ -152,17 +152,17 @@ system.physmem.wrQLenPdf::10 2909 # Wh system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 5885504293 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 50112950293 # Sum of mem lat for all requests -system.physmem.totBusLat 5900108000 # Total cycles spent in databus access -system.physmem.totBankLat 38327338000 # Total cycles spent in bank access -system.physmem.avgQLat 3990.10 # Average queueing delay per request -system.physmem.avgBankLat 25984.16 # Average bank access latency per request +system.physmem.totQLat 1657778750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15956610750 # Sum of mem lat for all requests +system.physmem.totBusLat 1904408000 # Total cycles spent in databus access +system.physmem.totBankLat 12394424000 # Total cycles spent in bank access +system.physmem.avgQLat 3481.98 # Average queueing delay per request +system.physmem.avgBankLat 26033.13 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33974.26 # Average memory access latency -system.physmem.avgRdBW 145.09 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 145.09 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.56 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 33515.11 # Average memory access latency +system.physmem.avgRdBW 47.37 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.66 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.95 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.08 # Average read queue length over time -system.physmem.avgWrQLen 10.99 # Average write queue length over time -system.physmem.readRowHits 824972 # Number of row buffer hits during reads -system.physmem.writeRowHits 37277 # Number of row buffer hits during writes -system.physmem.readRowHitRate 55.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.72 # Row buffer hit rate for writes -system.physmem.avgGap 422026.84 # Average gap between requests +system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.02 # Average read queue length over time +system.physmem.avgWrQLen 10.97 # Average write queue length over time +system.physmem.readRowHits 265466 # Number of row buffer hits during reads +system.physmem.writeRowHits 48780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 55.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.91 # Row buffer hit rate for writes +system.physmem.avgGap 1184632.05 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 526096858 # DTB read hits -system.cpu.dtb.read_misses 613073 # DTB read misses +system.cpu.dtb.read_hits 526069225 # DTB read hits +system.cpu.dtb.read_misses 579156 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526709931 # DTB read accesses -system.cpu.dtb.write_hits 292394059 # DTB write hits -system.cpu.dtb.write_misses 53899 # DTB write misses +system.cpu.dtb.read_accesses 526648381 # DTB read accesses +system.cpu.dtb.write_hits 297161949 # DTB write hits +system.cpu.dtb.write_misses 50214 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 292447958 # DTB write accesses -system.cpu.dtb.data_hits 818490917 # DTB hits -system.cpu.dtb.data_misses 666972 # DTB misses +system.cpu.dtb.write_accesses 297212163 # DTB write accesses +system.cpu.dtb.data_hits 823231174 # DTB hits +system.cpu.dtb.data_misses 629370 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 819157889 # DTB accesses -system.cpu.itb.fetch_hits 401734157 # ITB hits -system.cpu.itb.fetch_misses 1039 # ITB misses +system.cpu.dtb.data_accesses 823860544 # DTB accesses +system.cpu.itb.fetch_hits 405407805 # ITB hits +system.cpu.itb.fetch_misses 819 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 401735196 # ITB accesses +system.cpu.itb.fetch_accesses 405408624 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1304762689 # number of cpu cycles simulated +system.cpu.numCycles 1286719029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 395100113 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 257879210 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27591675 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 325941438 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262133239 # Number of BTB hits +system.cpu.BPredUnit.lookups 402098178 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 264077360 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27592144 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 331664988 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 265014495 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57700479 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6698 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421496575 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3322405570 # Number of instructions fetch has processed -system.cpu.fetch.Branches 395100113 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 319833718 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638480554 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162110923 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102053744 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9801 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 401734157 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8363180 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1296072068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.563442 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138795 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57783698 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7200 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 424132228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3367367633 # Number of instructions fetch has processed +system.cpu.fetch.Branches 402098178 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 322798193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 646196241 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 166511643 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 68824339 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9321 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 405407805 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9489583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1277592072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.635714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156498 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 657591514 50.74% 50.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60871982 4.70% 55.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44636510 3.44% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71794407 5.54% 64.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126302912 9.75% 74.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45673565 3.52% 77.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41643401 3.21% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7024748 0.54% 81.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 240533029 18.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 631395831 49.42% 49.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 61908546 4.85% 54.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 44955490 3.52% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72442913 5.67% 63.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127234893 9.96% 73.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45699485 3.58% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41229418 3.23% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8398105 0.66% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 244327391 19.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1296072068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302814 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546368 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 453815792 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84580008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 615145766 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8511561 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134018941 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 34684248 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12433 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3231024090 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46816 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134018941 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 483692761 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37815213 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 26926 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 592981976 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47536251 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3144588480 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1177 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7026 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41373292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2089769744 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3655475569 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3535468644 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120006925 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1277592072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312499 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.617019 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 452657714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55753482 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 621910588 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8852787 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 138417501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 35688961 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12608 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3272292546 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46854 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 138417501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 480561611 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 21495863 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27669 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 602513400 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 34576028 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3180651525 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 116 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 29849843 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2112719200 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3696606448 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3567977970 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128628478 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 704800674 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4226 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 127 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 142344309 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 735042012 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 359395829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68166545 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9320020 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2645223582 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 121 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2193823681 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17946245 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 822107127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 708225593 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1296072068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.692671 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.804037 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 727750130 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4257 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112675652 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 746614838 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 365012896 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68733869 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9300063 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2678263841 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 113 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2207816608 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17947963 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 855152506 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 736519407 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1277592072 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.728108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823912 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 475835975 36.71% 36.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 218666129 16.87% 53.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251350949 19.39% 72.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 122837911 9.48% 82.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105713044 8.16% 90.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 77520434 5.98% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21238629 1.64% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17216175 1.33% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5692822 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 463406335 36.27% 36.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 208221001 16.30% 52.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 253020667 19.80% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119517466 9.35% 81.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 107963864 8.45% 90.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79412827 6.22% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22155797 1.73% 98.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18005418 1.41% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5888697 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1296072068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1277592072 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1168166 3.19% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25201102 68.89% 72.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10214807 27.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146338 3.02% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26001591 68.56% 71.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10776371 28.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1258217376 57.35% 57.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16681 0.00% 57.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29224824 1.33% 58.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254695 0.38% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587046185 26.76% 86.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 303856512 13.85% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1263752223 57.24% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29225332 1.32% 58.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254699 0.37% 58.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 590734000 26.76% 86.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 308625853 13.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2193823681 # Type of FU issued -system.cpu.iq.rate 1.681397 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36584075 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016676 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5583657415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3378809764 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2023568909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 154592335 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88593840 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75404787 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2151259351 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 79145653 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62323542 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2207816608 # Type of FU issued +system.cpu.iq.rate 1.715850 # Inst issue rate +system.cpu.iq.fu_busy_cnt 37924300 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017177 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5591649635 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3435076999 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2032506919 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 157447916 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 98414178 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 76358311 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2164690748 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 81047408 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 59332604 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 223971986 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12645 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76017 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 148600933 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235544812 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11687 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 77448 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 154218000 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4436 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 69 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4399 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2001 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134018941 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11876310 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 832949 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3002252422 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2341492 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 735042012 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 359395829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187560 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4854 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76017 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27589712 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31349 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27621061 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2103239947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526710042 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90583734 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 138417501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7967616 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 401073 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3039337687 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 731219 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 746614838 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 365012896 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 113 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 191088 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1450 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 77448 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27584304 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31589 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27615893 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2113102879 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526648496 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94713729 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 357028719 # number of nop insts executed -system.cpu.iew.exec_refs 819158443 # number of memory reference insts executed -system.cpu.iew.exec_branches 282386049 # Number of branches executed -system.cpu.iew.exec_stores 292448401 # Number of stores executed -system.cpu.iew.exec_rate 1.611971 # Inst execution rate -system.cpu.iew.wb_sent 2101749466 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2098973696 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185216175 # num instructions producing a value -system.cpu.iew.wb_consumers 1752698092 # num instructions consuming a value +system.cpu.iew.exec_nop 361073733 # number of nop insts executed +system.cpu.iew.exec_refs 823861177 # number of memory reference insts executed +system.cpu.iew.exec_branches 283370996 # Number of branches executed +system.cpu.iew.exec_stores 297212681 # Number of stores executed +system.cpu.iew.exec_rate 1.642241 # Inst execution rate +system.cpu.iew.wb_sent 2111610495 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2108865230 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1193923515 # num instructions producing a value +system.cpu.iew.wb_consumers 1771725000 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.608702 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.676224 # average fanout of values written-back +system.cpu.iew.wb_rate 1.638948 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673876 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 976452699 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1013373341 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27579406 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1162053127 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.728826 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.486115 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27579934 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1139174571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.763547 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.475615 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 542846661 46.71% 46.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 230306455 19.82% 66.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119679848 10.30% 76.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 57176464 4.92% 81.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50189917 4.32% 86.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25112757 2.16% 88.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18284566 1.57% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15890460 1.37% 91.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102565999 8.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 512941432 45.03% 45.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 233024401 20.46% 65.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 122205483 10.73% 76.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58495999 5.13% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 54572847 4.79% 86.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24070176 2.11% 88.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18202956 1.60% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17085980 1.50% 91.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98575297 8.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1162053127 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1139174571 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,358 +475,374 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102565999 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98575297 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4039291021 # The number of ROB reads -system.cpu.rob.rob_writes 6104902002 # The number of ROB writes -system.cpu.timesIdled 33492 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8690621 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4057323809 # The number of ROB reads +system.cpu.rob.rob_writes 6183141843 # The number of ROB writes +system.cpu.timesIdled 212566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9126957 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.715706 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.715706 # CPI: Total CPI of All Threads -system.cpu.ipc 1.397222 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.397222 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2679345799 # number of integer regfile reads -system.cpu.int_regfile_writes 1518234716 # number of integer regfile writes -system.cpu.fp_regfile_reads 81979255 # number of floating regfile reads -system.cpu.fp_regfile_writes 54034777 # number of floating regfile writes +system.cpu.cpi 0.705808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.705808 # CPI: Total CPI of All Threads +system.cpu.ipc 1.416815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.416815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2692001611 # number of integer regfile reads +system.cpu.int_regfile_writes 1522401675 # number of integer regfile writes +system.cpu.fp_regfile_reads 82933521 # number of floating regfile reads +system.cpu.fp_regfile_writes 54035244 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8417 # number of replacements -system.cpu.icache.tagsinuse 1668.126238 # Cycle average of tags in use -system.cpu.icache.total_refs 401722811 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10139 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39621.541671 # Average number of references to valid blocks. +system.cpu.icache.replacements 8405 # number of replacements +system.cpu.icache.tagsinuse 1669.043453 # Cycle average of tags in use +system.cpu.icache.total_refs 405395000 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10125 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 40039.012346 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1668.126238 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.814515 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.814515 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 401722811 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 401722811 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 401722811 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 401722811 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 401722811 # number of overall hits -system.cpu.icache.overall_hits::total 401722811 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11346 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11346 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11346 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11346 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11346 # number of overall misses -system.cpu.icache.overall_misses::total 11346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 190399000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 190399000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 190399000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 190399000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 190399000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 190399000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 401734157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 401734157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 401734157 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 401734157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 401734157 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 401734157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16781.156355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16781.156355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16781.156355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16781.156355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16781.156355 # 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miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24210.386490 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24210.386490 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24210.386490 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24210.386490 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24210.386490 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24210.386490 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1240 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # 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number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10140 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10140 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10140 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10140 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 134814500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 134814500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 134814500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 134814500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 134814500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 134814500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2679 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23007.455955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527641 # number of replacements -system.cpu.dcache.tagsinuse 4095.118942 # Cycle average of tags in use -system.cpu.dcache.total_refs 671579546 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531737 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 438.443118 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 234314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.118942 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999785 # 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number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1059796 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1059796 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2984174 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2984174 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2984174 # number of overall misses -system.cpu.dcache.overall_misses::total 2984174 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77455395000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77455395000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 38159725987 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 38159725987 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115615120987 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115615120987 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92855043859 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92855043859 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92855043859 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92855043859 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 466730361 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 466730361 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 674563676 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 674563676 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 674563676 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 674563676 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004149 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004149 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005028 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005028 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004424 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004424 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004424 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004424 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40249.574148 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40249.574148 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36006.671083 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36006.671083 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38742.754607 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38742.754607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38742.754607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38742.754607 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 411 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 57 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 45 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 45 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 677525257 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 677525257 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 677525257 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 677525257 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004126 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004126 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.022222 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.022222 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004409 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004409 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004409 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004409 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30753.560758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30753.560758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31674.314118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31674.314118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31080.770085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31080.770085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12002 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 360 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.833333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.338889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109439 # number of writebacks -system.cpu.dcache.writebacks::total 109439 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 464250 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 464250 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 988187 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 988187 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1452437 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1452437 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1452437 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1452437 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460128 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39126904500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39126904500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39126904500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003129 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002271 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002271 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002271 # 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mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.022222 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24270.928058 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24270.928058 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51326.789129 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51326.789129 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 49000 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 71641 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71641 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1532229 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1542355 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1532229 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1542355 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.276812 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278319 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933167 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933167 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.276812 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.308947 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308736 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.276812 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.308947 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308736 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53373.528362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57679.226370 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57649.741772 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53205.757408 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53205.757408 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53373.528362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57047.458902 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 57025.832614 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53373.528362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57047.458902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 57025.832614 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 15.526316 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks -system.cpu.l2cache.writebacks::total 66898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2995 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409081 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1412076 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2995 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1475936 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1478931 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1475936 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1478931 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106523142 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49028505930 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 49135029072 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3470186582 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3470186582 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106523142 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 52498692512 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 52605215654 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106523142 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52498692512 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 52605215654 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965039 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.959176 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.959176 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.992321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34794.668248 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34796.306340 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51906.163817 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51906.163817 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks +system.cpu.l2cache.writebacks::total 66908 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2803 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406525 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66853 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66853 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473378 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476181 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473378 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476181 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 114329941 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18253645467 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18367975408 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2750960138 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2750960138 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114329941 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21004605605 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21118935546 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114329941 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21004605605 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21118935546 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278319 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933167 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933167 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308947 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308947 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308736 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40788.419907 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44901.655414 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44873.488762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41149.389526 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41149.389526 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40788.419907 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44371.740142 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44350.647224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40788.419907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44371.740142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44350.647224 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index a8bcfc08a..c58eb2bea 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.811836 # Number of seconds simulated -sim_ticks 2811836424000 # Number of ticks simulated -final_tick 2811836424000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.769740 # Number of seconds simulated +sim_ticks 2769739533000 # Number of ticks simulated +final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1325085 # Simulator instruction rate (inst/s) -host_op_rate 1325085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1854626286 # Simulator tick rate (ticks/s) -host_mem_usage 228472 # Number of bytes of host memory used -host_seconds 1516.12 # Real time elapsed on the host +host_inst_rate 1761560 # Simulator instruction rate (inst/s) +host_op_rate 1761559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2428616742 # Simulator tick rate (ticks/s) +host_mem_usage 226024 # Number of bytes of host memory used +host_seconds 1140.46 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94417856 # Number of bytes read from this memory -system.physmem.bytes_read::total 94569984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory -system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1475279 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33578716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33632818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54103 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54103 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1522660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1522660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1522660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33578716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35155479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory +system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5623672848 # number of cpu cycles simulated +system.cpu.numCycles 5539479066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5623672848 # Number of busy cycles +system.cpu.num_busy_cycles 5539479066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.427768 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.427768 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721889 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721889 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 237582000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 237582000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 237582000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 237582000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 237582000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 237582000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22421.857305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22421.857305 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.209846 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.209846 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999807 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999807 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78109548000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81853590000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81853590000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81853590000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81853590000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53566.024227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53566.024227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53494.043698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53494.043698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109771 # number of writebacks -system.cpu.dcache.writebacks::total 109771 # number of writebacks +system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks +system.cpu.dcache.writebacks::total 96129 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.474832 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29416.542403 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.099319 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.897722 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998062 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109771 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109771 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96129 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96129 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24718151000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24606195000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24718151000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 109771 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 109771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 96129 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 96129 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses @@ -328,28 +328,28 @@ system.cpu.l2cache.demand_accesses::total 1540740 # n system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965858 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.960508 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.203190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278648 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278104 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964144 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.959056 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964144 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.959056 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309249 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308520 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309249 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308520 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.007383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.007344 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.006311 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.006311 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks -system.cpu.l2cache.writebacks::total 66898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1408406 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1410783 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks +system.cpu.l2cache.writebacks::total 66908 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406323 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408476 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1475279 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1477656 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1475279 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1477656 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56336240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56431320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473196 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 475349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473196 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 475349 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16252923000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16339043000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59011160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59106240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59011160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59106240000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965858 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960508 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18927843000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19013963000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18927843000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19013963000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278648 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278104 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.959056 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.959056 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308520 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308520 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 1e57970d1..ac8776e10 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.659992 # Number of seconds simulated -sim_ticks 659991928000 # Number of ticks simulated -final_tick 659991928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.635788 # Number of seconds simulated +sim_ticks 635788224000 # Number of ticks simulated +final_tick 635788224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102750 # Simulator instruction rate (inst/s) -host_op_rate 139931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48985343 # Simulator tick rate (ticks/s) -host_mem_usage 254632 # Number of bytes of host memory used -host_seconds 13473.25 # Real time elapsed on the host -sim_insts 1384374560 # Number of instructions simulated -sim_ops 1885329312 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 198528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94517696 # Number of bytes read from this memory -system.physmem.bytes_read::total 94716224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 198528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 198528 # Number of instructions bytes read from this memory +host_inst_rate 107590 # Simulator instruction rate (inst/s) +host_op_rate 146523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49411882 # Simulator tick rate (ticks/s) +host_mem_usage 254872 # Number of bytes of host memory used +host_seconds 12867.11 # Real time elapsed on the host +sim_insts 1384378595 # Number of instructions simulated +sim_ops 1885333347 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 160512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30246144 # Number of bytes read from this memory +system.physmem.bytes_read::total 30406656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 160512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 160512 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3102 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2508 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472596 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475104 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 300804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 143210382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 143511185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 300804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 300804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6409581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6409581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6409581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 300804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 143210382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 149920767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1479941 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 252461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47572671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47825132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 252461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6653587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6653587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6653587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 252461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47572671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54478719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 475105 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 1550203 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 94716224 # Total number of bytes read from memory +system.physmem.cpureqs 545524 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30406656 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 94716224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30406656 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4222 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4164 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 92954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 91941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 92050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 91689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 92209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 92061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 92149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 92666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 91875 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 92213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 92439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 92957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 92247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 91863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 92572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 91834 # Track reads on a per bank basis +system.physmem.servicedByWrQ 162 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4321 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29801 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29611 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4108 # Tr system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 659991863500 # Total gap between requests +system.physmem.totGap 635788203500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1479941 # Categorize read packet sizes +system.physmem.readPktSize::6 475105 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,18 +102,18 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4164 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4321 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1408404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2873 # Wh system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 5597502027 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 50332290027 # Sum of mem lat for all requests -system.physmem.totBusLat 5902876000 # Total cycles spent in databus access -system.physmem.totBankLat 38831912000 # Total cycles spent in bank access -system.physmem.avgQLat 3793.07 # Average queueing delay per request -system.physmem.avgBankLat 26313.89 # Average bank access latency per request +system.physmem.totQLat 2296699471 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17086173471 # Sum of mem lat for all requests +system.physmem.totBusLat 1899772000 # Total cycles spent in databus access +system.physmem.totBankLat 12889702000 # Total cycles spent in bank access +system.physmem.avgQLat 4835.74 # Average queueing delay per request +system.physmem.avgBankLat 27139.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34106.96 # Average memory access latency -system.physmem.avgRdBW 143.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.41 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 143.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.41 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 35975.21 # Average memory access latency +system.physmem.avgRdBW 47.83 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.65 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.83 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.65 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.94 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.08 # Average read queue length over time -system.physmem.avgWrQLen 14.18 # Average write queue length over time -system.physmem.readRowHits 809039 # Number of row buffer hits during reads -system.physmem.writeRowHits 36662 # Number of row buffer hits during writes -system.physmem.readRowHitRate 54.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.47 # Row buffer hit rate for writes -system.physmem.avgGap 426892.12 # Average gap between requests +system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.03 # Average read queue length over time +system.physmem.avgWrQLen 17.42 # Average write queue length over time +system.physmem.readRowHits 249227 # Number of row buffer hits during reads +system.physmem.writeRowHits 48069 # Number of row buffer hits during writes +system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.72 # Row buffer hit rate for writes +system.physmem.avgGap 1174768.44 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,577 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1319983857 # number of cpu cycles simulated +system.cpu.numCycles 1271576449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 454350981 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 358310478 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33373061 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 312072233 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 240275028 # Number of BTB hits +system.cpu.BPredUnit.lookups 450228409 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 355532784 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 33221025 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 286250905 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 237054856 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53876645 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2808673 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 374001286 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2331861224 # Number of instructions fetch has processed -system.cpu.fetch.Branches 454350981 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 294151673 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 622796021 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 170528608 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 135818762 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 24217 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 352463772 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11980006 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1269746213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.542801 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.164977 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 53630453 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2814194 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 368782120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2317566621 # Number of instructions fetch has processed +system.cpu.fetch.Branches 450228409 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 290685309 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 618187609 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 167802769 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 122950545 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 34033 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 346967374 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10833079 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1244485983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575716 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.174798 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 646995456 50.95% 50.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44687712 3.52% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 102379693 8.06% 62.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59922071 4.72% 67.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 74129472 5.84% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45582835 3.59% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31361893 2.47% 79.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30601811 2.41% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 234085270 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 626344117 50.33% 50.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 45317842 3.64% 53.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101227769 8.13% 62.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 59470859 4.78% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 73017121 5.87% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44727211 3.59% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30024154 2.41% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31448495 2.53% 81.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232908415 18.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1269746213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.344209 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.766583 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 425403268 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107718588 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 581478902 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18055452 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 137090003 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 51078179 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15137 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3127640414 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28961 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 137090003 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 461511464 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39177126 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 530700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 561763722 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69673198 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3042064401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 391 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4490697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56029467 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2572 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2999547883 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14489457877 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13880825981 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 608631896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993146442 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1006401441 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25504 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 180658895 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 975543094 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 514319343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 34765547 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38827815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2864053634 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 32821 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2484775177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 12535683 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 966091505 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2435627475 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10643 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1269746213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886378 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1244485983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.354071 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.822593 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 419135073 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95311788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 577111124 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18421558 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134506440 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 50263790 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 26327 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3103411757 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 60284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134506440 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 455352486 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27182944 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 495803 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 558181591 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68766719 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3020461835 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1786182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58542729 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2987223490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14381793689 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13781741718 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 600051971 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993152898 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 994070592 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23484 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 177920569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971527729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 505697139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 29364054 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38323451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2844663565 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34202 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2471693501 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 7154025 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 946732451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2394075214 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11217 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1244485983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.986116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 414113290 32.61% 32.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 194811826 15.34% 47.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 206120235 16.23% 64.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171548762 13.51% 77.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 130841431 10.30% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97116191 7.65% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37554058 2.96% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12317792 0.97% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5322628 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 394145382 31.67% 31.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 193214413 15.53% 47.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204405304 16.42% 63.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171173190 13.75% 77.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 129740055 10.43% 87.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 97310600 7.82% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 36398713 2.92% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12543196 1.01% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5555130 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1269746213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1244485983 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 947301 1.02% 1.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24145 0.03% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56191268 60.42% 61.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35841535 38.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 746380 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24393 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55867065 61.34% 62.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 34441237 37.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1133457764 45.62% 45.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11237396 0.45% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876496 0.28% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5506177 0.22% 46.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23536328 0.95% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838863420 33.76% 81.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 463922306 18.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1129092447 45.68% 45.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11228574 0.45% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501982 0.22% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23586280 0.95% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 837187213 33.87% 81.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 456845236 18.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2484775177 # Type of FU issued -system.cpu.iq.rate 1.882428 # Inst issue rate -system.cpu.iq.fu_busy_cnt 93004249 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.037430 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6215984950 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3740236476 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2293829225 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128851549 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 90009348 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59026271 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2510712861 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 67066565 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78532237 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2471693501 # Type of FU issued +system.cpu.iq.rate 1.943803 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91079075 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036849 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6158633993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704145010 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2281572785 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 127472092 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 87353789 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58523777 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2496546302 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66226274 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 80772254 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 344155119 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5694 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1300004 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 237323252 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340138947 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 411099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 228700241 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 137090003 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17084434 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1439762 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2864100864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 11154453 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 975543094 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 514319343 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22441 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1430096 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1300004 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 35278606 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1697024 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36975630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2406030122 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 793312488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78745055 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134506440 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8643138 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 547079 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2844711818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 10610498 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971527729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 505697139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23185 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 540297 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 411099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 34712988 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1840552 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 36553540 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2395281486 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 793221583 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 76412015 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14409 # number of nop insts executed -system.cpu.iew.exec_refs 1235149676 # number of memory reference insts executed -system.cpu.iew.exec_branches 329779468 # Number of branches executed -system.cpu.iew.exec_stores 441837188 # Number of stores executed -system.cpu.iew.exec_rate 1.822772 # Inst execution rate -system.cpu.iew.wb_sent 2378266547 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2352855496 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1358943525 # num instructions producing a value -system.cpu.iew.wb_consumers 2560958188 # num instructions consuming a value +system.cpu.iew.exec_nop 14051 # number of nop insts executed +system.cpu.iew.exec_refs 1229345389 # number of memory reference insts executed +system.cpu.iew.exec_branches 327128098 # Number of branches executed +system.cpu.iew.exec_stores 436123806 # Number of stores executed +system.cpu.iew.exec_rate 1.883710 # Inst execution rate +system.cpu.iew.wb_sent 2368179118 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2340096562 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1354502475 # num instructions producing a value +system.cpu.iew.wb_consumers 2541864992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.782488 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.530639 # average fanout of values written-back +system.cpu.iew.wb_rate 1.840311 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.532877 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 978761117 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22178 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33359188 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1132656212 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.664530 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.366367 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 959367728 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22985 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 33197953 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1109979545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.698540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.378671 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 484847147 42.81% 42.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 300235204 26.51% 69.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 89818902 7.93% 77.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 73190759 6.46% 83.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44951546 3.97% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23093029 2.04% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848859 1.40% 91.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9835568 0.87% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90835198 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 463287159 41.74% 41.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 297974077 26.85% 68.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91457957 8.24% 76.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72253905 6.51% 83.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45208298 4.07% 87.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23225084 2.09% 89.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15854658 1.43% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10141159 0.91% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90577248 8.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1132656212 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384385576 # Number of instructions committed -system.cpu.commit.committedOps 1885340328 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1109979545 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384389611 # Number of instructions committed +system.cpu.commit.committedOps 1885344363 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908384066 # Number of memory references committed -system.cpu.commit.loads 631387975 # Number of loads committed +system.cpu.commit.refs 908385680 # Number of memory references committed +system.cpu.commit.loads 631388782 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299635189 # Number of branches committed +system.cpu.commit.branches 299635996 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653702043 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705271 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90835198 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90577248 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3905904114 # The number of ROB reads -system.cpu.rob.rob_writes 5865307964 # The number of ROB writes -system.cpu.timesIdled 1232544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50237644 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384374560 # Number of Instructions Simulated -system.cpu.committedOps 1885329312 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384374560 # Number of Instructions Simulated -system.cpu.cpi 0.953488 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.953488 # CPI: Total CPI of All Threads -system.cpu.ipc 1.048781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.048781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11951457171 # number of integer regfile reads -system.cpu.int_regfile_writes 2254061534 # number of integer regfile writes -system.cpu.fp_regfile_reads 71109797 # number of floating regfile reads -system.cpu.fp_regfile_writes 50119198 # number of floating regfile writes -system.cpu.misc_regfile_reads 3727888158 # number of misc regfile reads -system.cpu.misc_regfile_writes 13774490 # number of misc regfile writes -system.cpu.icache.replacements 23076 # number of replacements -system.cpu.icache.tagsinuse 1653.132974 # Cycle average of tags in use -system.cpu.icache.total_refs 352429997 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24765 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14230.971007 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3864096043 # The number of ROB reads +system.cpu.rob.rob_writes 5823945497 # The number of ROB writes +system.cpu.timesIdled 351641 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27090466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384378595 # Number of Instructions Simulated +system.cpu.committedOps 1885333347 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384378595 # Number of Instructions Simulated +system.cpu.cpi 0.918518 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.918518 # CPI: Total CPI of All Threads +system.cpu.ipc 1.088710 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.088710 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11907054979 # number of integer regfile reads +system.cpu.int_regfile_writes 2251695031 # number of integer regfile writes +system.cpu.fp_regfile_reads 70501707 # number of floating regfile reads +system.cpu.fp_regfile_writes 50326111 # number of floating regfile writes +system.cpu.misc_regfile_reads 3707678526 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776104 # number of misc regfile writes +system.cpu.icache.replacements 23916 # number of replacements +system.cpu.icache.tagsinuse 1661.487549 # Cycle average of tags in use +system.cpu.icache.total_refs 346930644 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 25614 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13544.571094 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1653.132974 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.807194 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.807194 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 352434103 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 352434103 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 352434103 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 352434103 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 352434103 # number of overall hits -system.cpu.icache.overall_hits::total 352434103 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 29669 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 29669 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 29669 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 29669 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 29669 # number of overall misses -system.cpu.icache.overall_misses::total 29669 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 256567500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 256567500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 256567500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 256567500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 256567500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 256567500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 352463772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 352463772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 352463772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 352463772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 352463772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 352463772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8647.662543 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8647.662543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8647.662543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8647.662543 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1661.487549 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.811273 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.811273 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 346934721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 346934721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 346934721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 346934721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 346934721 # number of overall hits +system.cpu.icache.overall_hits::total 346934721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 32652 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 32652 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 32652 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 32652 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 32652 # number of overall misses +system.cpu.icache.overall_misses::total 32652 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 492196499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 492196499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 492196499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 492196499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 492196499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 492196499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 346967373 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 346967373 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 346967373 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 346967373 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 346967373 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 346967373 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15074.007687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15074.007687 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15074.007687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15074.007687 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1459 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.685714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 738 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 738 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 738 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 738 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 738 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 738 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28931 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28931 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28931 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28931 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28931 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28931 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178433000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178433000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6167.536552 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6167.536552 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2714 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2714 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2714 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2714 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2714 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2714 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29938 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 29938 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 29938 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 29938 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 29938 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 29938 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 396628999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 396628999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 396628999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 396628999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 396628999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 396628999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13248.346550 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13248.346550 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533235 # number of replacements -system.cpu.dcache.tagsinuse 4094.869938 # Cycle average of tags in use -system.cpu.dcache.total_refs 976399177 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537331 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 635.126188 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 278705000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.869938 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999724 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999724 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 700249991 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 700249991 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276118441 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276118441 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11312 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11312 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10779 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10779 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 976368432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 976368432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 976368432 # number of overall hits -system.cpu.dcache.overall_hits::total 976368432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2072491 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2072491 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 817237 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 817237 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 10 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 10 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2889728 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2889728 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2889728 # number of overall misses -system.cpu.dcache.overall_misses::total 2889728 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84515499000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84515499000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31029320000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31029320000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 296000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115544819000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115544819000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 115544819000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 115544819000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 702322482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 702322482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533079 # number of replacements +system.cpu.dcache.tagsinuse 4094.602102 # Cycle average of tags in use +system.cpu.dcache.total_refs 974126836 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 633.712385 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 342496000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.602102 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999659 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999659 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 697989238 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 697989238 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276101323 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276101323 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 12267 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 12267 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11586 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11586 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 974090561 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 974090561 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 974090561 # number of overall hits +system.cpu.dcache.overall_hits::total 974090561 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2001936 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2001936 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 834355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 834355 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2836291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2836291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2836291 # number of overall misses +system.cpu.dcache.overall_misses::total 2836291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68815075500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68815075500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39938491970 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39938491970 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 108753567470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 108753567470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 108753567470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 108753567470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 699991174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 699991174 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11322 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11322 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10779 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10779 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 979258160 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 979258160 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 979258160 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 979258160 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002951 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000883 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000883 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40779.669972 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40779.669972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37968.569705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37968.569705 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29600 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29600 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39984.669491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39984.669491 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21.500000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11586 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11586 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 976926852 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 976926852 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 976926852 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 976926852 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002860 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002860 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003013 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003013 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000163 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000163 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002903 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002903 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002903 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002903 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34374.263463 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34374.263463 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47867.504803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47867.504803 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38343.585856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38343.585856 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1801 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 752 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 85 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.016667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.847059 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108671 # number of writebacks -system.cpu.dcache.writebacks::total 108671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 607721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 607721 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 740509 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 10 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 10 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1348230 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1348230 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1348230 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1348230 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464770 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464770 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76728 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76728 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541498 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541498 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541498 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541498 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 56538138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 56538138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2635948000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2635948000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 59174086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 59174086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 59174086500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 59174086500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002086 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002086 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001574 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001574 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001574 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001574 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38598.645862 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38598.645862 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34354.446877 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34354.446877 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 96247 # number of writebacks +system.cpu.dcache.writebacks::total 96247 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 537314 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 537314 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 757477 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1294791 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1294791 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1294791 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1294791 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464622 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464622 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76878 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76878 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541500 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541500 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541500 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541500 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36879858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36879858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3477356000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3477356000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40357214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40357214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40357214500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40357214500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002092 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002092 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001578 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001578 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25180.461921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25180.461921 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45232.134031 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45232.134031 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480138 # number of replacements -system.cpu.l2cache.tagsinuse 32697.181297 # Cycle average of tags in use -system.cpu.l2cache.total_refs 84298 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512881 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.055720 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442324 # number of replacements +system.cpu.l2cache.tagsinuse 32688.980204 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1110893 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 475069 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.338382 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3151.564148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 56.407826 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29489.209323 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.096178 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001721 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.899939 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997839 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21652 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 53983 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19690336164 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19789779555 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43223820 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43223820 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2389121519 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2389121519 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99443391 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22079457683 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22178901074 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99443391 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22079457683 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22178901074 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274471 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999306 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999306 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910742 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910742 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304011 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304011 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39634.671582 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48436.566558 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48382.575123 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.198334 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.198334 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36156.080980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36156.080980 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 1b9ad306d..ac5d108eb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.368273 # Number of seconds simulated -sim_ticks 2368273403000 # Number of ticks simulated -final_tick 2368273403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.326119 # Number of seconds simulated +sim_ticks 2326118592000 # Number of ticks simulated +final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 821983 # Simulator instruction rate (inst/s) -host_op_rate 1115078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1408999350 # Simulator tick rate (ticks/s) -host_mem_usage 241788 # Number of bytes of host memory used -host_seconds 1680.82 # Real time elapsed on the host +host_inst_rate 541548 # Simulator instruction rate (inst/s) +host_op_rate 734649 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 911769830 # Simulator tick rate (ticks/s) +host_mem_usage 240408 # Number of bytes of host memory used +host_seconds 2551.21 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94437440 # Number of bytes read from this memory -system.physmem.bytes_read::total 94581888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory +system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1475585 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39876072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39937065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1786253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1786253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1786253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39876072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41723318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4736546806 # number of cpu cycles simulated +system.cpu.numCycles 4652237184 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1381604339 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 908382479 # nu system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4736546806 # Number of busy cycles +system.cpu.num_busy_cycles 4652237184 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.329214 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1392.317060 # Cycle average of tags in use system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.329214 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.679848 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.679848 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.679842 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 19803 # n system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 352238000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 352238000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 352238000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 352238000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 352238000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 352238000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17787.102964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17787.102964 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 19803 system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312632000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312632000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312632000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312632000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312632000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312632000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.965929 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.965929 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999748 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999748 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78190013000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78190013000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81912059000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81912059000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81912059000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81912059000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53409.773267 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53409.773267 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109047 # number of writebacks -system.cpu.dcache.writebacks::total 109047 # number of writebacks +system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks +system.cpu.dcache.writebacks::total 96257 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1478696 # number of replacements -system.cpu.l2cache.tagsinuse 32690.092056 # Cycle average of tags in use -system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 441378 # number of replacements +system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 474121 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.325596 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3194.112587 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.917167 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29463.062302 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.097477 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.899141 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997622 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109047 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109047 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96257 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96257 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17546 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 58068 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 75614 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17546 # 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number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 1553456 # n system.cpu.l2cache.overall_accesses::cpu.inst 19803 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964829 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.953449 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.089532 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278115 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.275592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.962137 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.951325 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.215330 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.089532 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.308012 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.305227 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.089532 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.308012 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59023400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59113685000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70926000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18895320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18966246000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70926000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18895320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18966246000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278115 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.275592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.305227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |