regressions: stats update due to decoder changes

1 files changed, 132 insertions, 132 deletions

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 65535d511..2c9a2891f 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.624868                       # Nu
 sim_ticks                                624867585500                       # Number of ticks simulated
 final_tick                               624867585500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  92987                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126636                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               41971725                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253512                       # Number of bytes of host memory used
-host_seconds                                 14887.82                       # Real time elapsed on the host
+host_inst_rate                                 118271                       # Simulator instruction rate (inst/s)
+host_op_rate                                   161069                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53384157                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298364                       # Number of bytes of host memory used
+host_seconds                                 11705.11                       # Real time elapsed on the host
 sim_insts                                  1384379060                       # Number of instructions simulated
 sim_ops                                    1885333812                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            155584                       # Number of bytes read from this memory
@@ -502,7 +502,7 @@ system.cpu.int_regfile_reads              11770471325                       # nu
 system.cpu.int_regfile_writes              2224868034                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                  68796296                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                 49549961                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              3658188004                       # number of misc regfile reads
+system.cpu.misc_regfile_reads              1363964167                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               13776290                       # number of misc regfile writes
 system.cpu.icache.replacements                  22546                       # number of replacements
 system.cpu.icache.tagsinuse               1642.542137                       # Cycle average of tags in use
@@ -588,6 +588,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                1532987                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.606879                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                970022641                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1537083                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 631.080196                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              335185000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.606879                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999660                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999660                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    693885026                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       693885026                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    276101075                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      276101075                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        11981                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        11981                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        11679                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        11679                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     969986101                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        969986101                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    969986101                       # number of overall hits
+system.cpu.dcache.overall_hits::total       969986101                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1953380                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1953380                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       834603                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       834603                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2787983                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2787983                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2787983                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2787983                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  67369161000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  67369161000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  39954942470                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  39954942470                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       199000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       199000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 107324103470                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 107324103470                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 107324103470                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 107324103470                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    695838406                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    695838406                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11984                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        11984                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        11679                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        11679                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    972774084                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    972774084                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    972774084                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    972774084                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002807                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002807                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003014                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.003014                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000250                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000250                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002866                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002866                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002866                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002866                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38495.250319                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38495.250319                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1740                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          681                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                55                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              87                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.636364                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.827586                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks        96322                       # number of writebacks
+system.cpu.dcache.writebacks::total             96322                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       488810                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       488810                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       757757                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       757757                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1246567                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1246567                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1246567                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1246567                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464570                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1464570                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76846                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        76846                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1541416                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1541416                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1541416                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1541416                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  37884239500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  37884239500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3478488500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3478488500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41362728000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  41362728000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41362728000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  41362728000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002105                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002105                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000277                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000277                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.001585                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001585                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                442193                       # number of replacements
 system.cpu.l2cache.tagsinuse             32688.524201                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1109720                       # Total number of references to valid blocks.
@@ -751,131 +877,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1532987                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.606879                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                970022641                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1537083                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 631.080196                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              335185000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.606879                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999660                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999660                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    693885026                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       693885026                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    276101075                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      276101075                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        11981                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        11981                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        11679                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        11679                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     969986101                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        969986101                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    969986101                       # number of overall hits
-system.cpu.dcache.overall_hits::total       969986101                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1953380                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1953380                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       834603                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       834603                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2787983                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2787983                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2787983                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2787983                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  67369161000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  67369161000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  39954942470                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  39954942470                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       199000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       199000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 107324103470                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 107324103470                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 107324103470                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 107324103470                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    695838406                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    695838406                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11984                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        11984                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        11679                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        11679                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    972774084                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    972774084                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    972774084                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    972774084                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002807                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002807                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003014                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.003014                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000250                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000250                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002866                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002866                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002866                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002866                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38495.250319                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38495.250319                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1740                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          681                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                55                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              87                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.636364                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.827586                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        96322                       # number of writebacks
-system.cpu.dcache.writebacks::total             96322                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       488810                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       488810                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       757757                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       757757                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1246567                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1246567                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1246567                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1246567                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464570                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1464570                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76846                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        76846                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1541416                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1541416                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1541416                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1541416                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  37884239500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  37884239500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3478488500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3478488500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41362728000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  41362728000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41362728000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  41362728000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002105                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002105                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000277                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000277                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001585                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001585                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------