diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/40.perlbmk | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/40.perlbmk')
4 files changed, 2769 insertions, 2692 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index fb73a0a48..a78600dd4 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.560955 # Number of seconds simulated -sim_ticks 560955232000 # Number of ticks simulated -final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.504258 # Number of seconds simulated +sim_ticks 504258263000 # Number of ticks simulated +final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 326346 # Simulator instruction rate (inst/s) -host_op_rate 326346 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197101410 # Simulator tick rate (ticks/s) -host_mem_usage 309500 # Number of bytes of host memory used -host_seconds 2846.02 # Real time elapsed on the host +host_inst_rate 397765 # Simulator instruction rate (inst/s) +host_op_rate 397765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215954385 # Simulator tick rate (ticks/s) +host_mem_usage 262596 # Number of bytes of host memory used +host_seconds 2335.02 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 184896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18519872 # Number of bytes read from this memory -system.physmem.bytes_read::total 18704768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 184896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 184896 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory +system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185088 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289373 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292267 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 329609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33014884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33344493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 329609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 329609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7607937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7607937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7607937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 329609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33014884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40952430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292262 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 367050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36727212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37094262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 367050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 367050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8463346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8463346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8463346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 367050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36727212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 45557607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292267 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292262 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292267 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18684608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18704768 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18685248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18705088 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18033 # Per bank write bursts -system.physmem.perBankRdBursts::1 18359 # Per bank write bursts +system.physmem.perBankRdBursts::1 18363 # Per bank write bursts system.physmem.perBankRdBursts::2 18394 # Per bank write bursts -system.physmem.perBankRdBursts::3 18332 # Per bank write bursts -system.physmem.perBankRdBursts::4 18249 # Per bank write bursts -system.physmem.perBankRdBursts::5 18255 # Per bank write bursts -system.physmem.perBankRdBursts::6 18314 # Per bank write bursts -system.physmem.perBankRdBursts::7 18296 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18236 # Per bank write bursts +system.physmem.perBankRdBursts::3 18341 # Per bank write bursts +system.physmem.perBankRdBursts::4 18245 # Per bank write bursts +system.physmem.perBankRdBursts::5 18249 # Per bank write bursts +system.physmem.perBankRdBursts::6 18313 # Per bank write bursts +system.physmem.perBankRdBursts::7 18290 # Per bank write bursts +system.physmem.perBankRdBursts::8 18231 # Per bank write bursts +system.physmem.perBankRdBursts::9 18232 # Per bank write bursts system.physmem.perBankRdBursts::10 18229 # Per bank write bursts system.physmem.perBankRdBursts::11 18376 # Per bank write bursts -system.physmem.perBankRdBursts::12 18263 # Per bank write bursts -system.physmem.perBankRdBursts::13 18132 # Per bank write bursts -system.physmem.perBankRdBursts::14 18061 # Per bank write bursts -system.physmem.perBankRdBursts::15 18191 # Per bank write bursts +system.physmem.perBankRdBursts::12 18272 # Per bank write bursts +system.physmem.perBankRdBursts::13 18137 # Per bank write bursts +system.physmem.perBankRdBursts::14 18064 # Per bank write bursts +system.physmem.perBankRdBursts::15 18188 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts +system.physmem.perBankWrBursts::9 4183 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 560955150000 # Total gap between requests +system.physmem.totGap 504258181000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292262 # Read request sizes (log2) +system.physmem.readPktSize::6 292267 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4051 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,121 +193,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 220.533003 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.789866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.043159 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 38344 36.85% 36.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 44004 42.28% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8921 8.57% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 721 0.69% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1372 1.32% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1145 1.10% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 668 0.64% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 598 0.57% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8294 7.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104067 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.768889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.564435 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 763.185509 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.78% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 103155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.473443 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.311324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.647767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37345 36.20% 36.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43741 42.40% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9241 8.96% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 735 0.71% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1396 1.35% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1157 1.12% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 662 0.64% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 564 0.55% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8314 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103155 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.893801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.549322 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 747.524050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4050 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4050 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.461235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.440549 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.842853 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3116 76.94% 76.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 76.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 932 23.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4050 # Writes before turning the bus around for reads -system.physmem.totQLat 2934449500 # Total ticks spent queuing -system.physmem.totMemAccLat 8408455750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459735000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10051.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463077 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.442287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.845052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 933 23.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads +system.physmem.totQLat 3567632750 # Total ticks spent queuing +system.physmem.totMemAccLat 9041826500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12219.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28801.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30969.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 37.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 37.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.32 # Data bus utilization in percentage -system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing -system.physmem.readRowHits 202530 # Number of row buffer hits during reads -system.physmem.writeRowHits 52011 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes -system.physmem.avgGap 1562788.59 # Average gap between requests -system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140391200 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing +system.physmem.readRowHits 203404 # Number of row buffer hits during reads +system.physmem.writeRowHits 52048 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes +system.physmem.avgGap 1404814.55 # Average gap between requests +system.physmem.pageHitRate 71.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 388939320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 212218875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140243000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109486358955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240531047250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388619465820 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.784540 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 399461576500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18731440000 # Time in different power states +system.physmem_0.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 104730111945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 210683510250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 350306824590 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.703966 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 349825620000 # Time in different power states +system.physmem_0.memoryStateTime::REF 16838120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142759852250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 137589656250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 394276680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 215131125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136522400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109506441195 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240513431250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388620069450 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.785616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399429681750 # Time in different power states -system.physmem_1.memoryStateTime::REF 18731440000 # Time in different power states +system.physmem_1.actEnergy 390829320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 213250125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136538000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215511840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105447215835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 210054471750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 350393179590 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.875219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 348773258750 # Time in different power states +system.physmem_1.memoryStateTime::REF 16838120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 142792236250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125747709 # Number of BP lookups -system.cpu.branchPred.condPredicted 81143389 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12156447 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103980471 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83512685 # Number of BTB hits +system.cpu.branchPred.lookups 123840342 # Number of BP lookups +system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 102061444 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68186680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.315740 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691016 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 66.809441 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691358 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9446 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14052117 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14048642 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3475 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11780 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537764 # DTB read hits -system.cpu.dtb.read_misses 198464 # DTB read misses +system.cpu.dtb.read_hits 237538322 # DTB read hits +system.cpu.dtb.read_misses 198467 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736228 # DTB read accesses -system.cpu.dtb.write_hits 98304946 # DTB write hits -system.cpu.dtb.write_misses 7177 # DTB write misses +system.cpu.dtb.read_accesses 237736789 # DTB read accesses +system.cpu.dtb.write_hits 98305180 # DTB write hits +system.cpu.dtb.write_misses 7178 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312123 # DTB write accesses -system.cpu.dtb.data_hits 335842710 # DTB hits -system.cpu.dtb.data_misses 205641 # DTB misses +system.cpu.dtb.write_accesses 98312358 # DTB write accesses +system.cpu.dtb.data_hits 335843502 # DTB hits +system.cpu.dtb.data_misses 205645 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048351 # DTB accesses -system.cpu.itb.fetch_hits 316984906 # ITB hits -system.cpu.itb.fetch_misses 120 # ITB misses +system.cpu.dtb.data_accesses 336049147 # DTB accesses +system.cpu.itb.fetch_hits 285763790 # ITB hits +system.cpu.itb.fetch_misses 119 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316985026 # ITB accesses +system.cpu.itb.fetch_accesses 285763909 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,83 +325,118 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1121910464 # number of cpu cycles simulated +system.cpu.numCycles 1008516526 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30861351 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.207928 # CPI: cycles per instruction -system.cpu.ipc 0.827864 # IPC: instructions per cycle -system.cpu.tickCycles 1059707465 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62202999 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.085840 # CPI: cycles per instruction +system.cpu.ipc 0.920946 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction +system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction +system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction +system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 928789150 # Class of committed instruction +system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked +system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776530 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.728000 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322866540 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 898816500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.728000 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999201 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999201 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 411.972126 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 901583500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.342308 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999107 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 951 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1398 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648211872 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648211872 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224702494 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224702494 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164046 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322866540 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322866540 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322866540 # number of overall hits -system.cpu.dcache.overall_hits::total 322866540 # number of overall hits +system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 321596153 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 321596153 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 321596153 # number of overall hits +system.cpu.dcache.overall_hits::total 321596153 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137154 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849083 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849083 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849083 # number of overall misses -system.cpu.dcache.overall_misses::total 849083 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24904735500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24904735500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9954481000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9954481000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34859216500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34859216500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34859216500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34859216500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225414423 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225414423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses +system.cpu.dcache.overall_misses::total 849082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25457059500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25457059500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10110916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10110916000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35567975500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35567975500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35567975500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35567975500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 224144035 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 224144035 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323715623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323715623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323715623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323715623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 322445235 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 322445235 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 322445235 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 322445235 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003176 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41055.134186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41055.134186 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41889.918170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41889.918170 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,16 +445,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88497 # number of writebacks -system.cpu.dcache.writebacks::total 88497 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks +system.cpu.dcache.writebacks::total 88489 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68143 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68457 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68457 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68457 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68457 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -424,85 +463,85 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780626 system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24185998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24185998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4992658500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4992658500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29178656500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29178656500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29178656500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29178656500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24738054000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24738054000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5071007000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5071007000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29809061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29809061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29809061000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29809061000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003175 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003175 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002421 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002421 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10567 # number of replacements -system.cpu.icache.tags.tagsinuse 1685.376446 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316972597 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12308 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25753.379672 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12309 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23214.841173 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376446 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.822938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.822938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.158478 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823320 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823320 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633982120 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633982120 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316972597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316972597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316972597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316972597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316972597 # number of overall hits -system.cpu.icache.overall_hits::total 316972597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12309 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12309 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12309 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12309 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12309 # number of overall misses -system.cpu.icache.overall_misses::total 12309 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 349738000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 349738000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 349738000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 349738000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 349738000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 349738000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316984906 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316984906 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316984906 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316984906 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316984906 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316984906 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28413.193598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28413.193598 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285751480 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285751480 # number of overall hits +system.cpu.icache.overall_hits::total 285751480 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12310 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12310 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12310 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12310 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12310 # number of overall misses +system.cpu.icache.overall_misses::total 12310 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352350500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352350500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352350500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352350500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352350500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352350500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 285763790 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 285763790 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 285763790 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 285763790 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 285763790 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 285763790 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28623.111292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28623.111292 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,133 +552,133 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 10567 # number of writebacks system.cpu.icache.writebacks::total 10567 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12309 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12309 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12309 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12309 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12309 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12309 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 337430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 337430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337430000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 337430000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27413.274840 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27413.274840 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12310 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12310 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12310 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12310 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 340041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 340041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340041500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 340041500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259935 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32594.451091 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218218 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292671 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.162414 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259940 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292676 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.162330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2600.597713 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 77.726752 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29916.126627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.079364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002372 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.912968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994704 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2630.640415 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.297977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29869.711599 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.080281 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002420 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.911551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994252 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2660 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29372 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13001938 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13001938 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88497 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88497 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13001951 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20586193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20779973000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193779500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20586193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20779973000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.234788 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312989 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312989 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368584 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368584 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312992 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312992 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368590 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368590 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1580032 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2079 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2079 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 723923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881298 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12309 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12310 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35184 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35186 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2372966 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57087872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259935 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1052870 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001975 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044393 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 2372968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259940 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1052876 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001976 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044414 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050791 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2079 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050795 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2081 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052870 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889080000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052876 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889072500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18462000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18463500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225617 # Transaction distribution +system.membus.trans_dist::ReadResp 225622 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191173 # Transaction distribution +system.membus.trans_dist::CleanEvict 191176 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225617 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842380 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22972480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225622 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842393 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842393 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22972800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 550118 # Request fanout histogram +system.membus.snoop_fanout::samples 550126 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550118 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 550126 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550118 # Request fanout histogram -system.membus.reqLayer0.occupancy 918693000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 550126 # Request fanout histogram +system.membus.reqLayer0.occupancy 918516000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556459000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556053500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 72a187780..f6b6cbb05 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.276414 # Number of seconds simulated -sim_ticks 276414065500 # Number of ticks simulated -final_tick 276414065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.174766 # Number of seconds simulated +sim_ticks 174766258500 # Number of ticks simulated +final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168860 # Simulator instruction rate (inst/s) -host_op_rate 168860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55408638 # Simulator tick rate (ticks/s) -host_mem_usage 309496 # Number of bytes of host memory used -host_seconds 4988.65 # Real time elapsed on the host +host_inst_rate 293073 # Simulator instruction rate (inst/s) +host_op_rate 293073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60802944 # Simulator tick rate (ticks/s) +host_mem_usage 263360 # Number of bytes of host memory used +host_seconds 2874.31 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 172736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18523584 # Number of bytes read from this memory -system.physmem.bytes_read::total 18696320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 172736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 172736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289431 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292130 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 624918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 67013898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67638816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 624918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 624918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15439562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15439562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15439562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 624918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 67013898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 83078377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292130 # Number of read requests accepted -system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292130 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18675136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18696320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory +system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 174016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 174016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2719 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292166 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 995707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 105996479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106992186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 995707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 995707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24419176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24419176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24419176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 995707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 105996479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 131411362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292166 # Number of read requests accepted +system.physmem.writeReqs 66682 # Number of write requests accepted +system.physmem.readBursts 292166 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18677824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265792 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18698624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18006 # Per bank write bursts -system.physmem.perBankRdBursts::1 18321 # Per bank write bursts -system.physmem.perBankRdBursts::2 18379 # Per bank write bursts -system.physmem.perBankRdBursts::3 18333 # Per bank write bursts -system.physmem.perBankRdBursts::4 18240 # Per bank write bursts -system.physmem.perBankRdBursts::5 18219 # Per bank write bursts -system.physmem.perBankRdBursts::6 18314 # Per bank write bursts -system.physmem.perBankRdBursts::7 18303 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18223 # Per bank write bursts -system.physmem.perBankRdBursts::10 18219 # Per bank write bursts -system.physmem.perBankRdBursts::11 18380 # Per bank write bursts -system.physmem.perBankRdBursts::12 18258 # Per bank write bursts -system.physmem.perBankRdBursts::13 18122 # Per bank write bursts -system.physmem.perBankRdBursts::14 18052 # Per bank write bursts -system.physmem.perBankRdBursts::15 18198 # Per bank write bursts +system.physmem.perBankRdBursts::1 18334 # Per bank write bursts +system.physmem.perBankRdBursts::2 18382 # Per bank write bursts +system.physmem.perBankRdBursts::3 18340 # Per bank write bursts +system.physmem.perBankRdBursts::4 18235 # Per bank write bursts +system.physmem.perBankRdBursts::5 18233 # Per bank write bursts +system.physmem.perBankRdBursts::6 18311 # Per bank write bursts +system.physmem.perBankRdBursts::7 18302 # Per bank write bursts +system.physmem.perBankRdBursts::8 18233 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18220 # Per bank write bursts +system.physmem.perBankRdBursts::11 18388 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18125 # Per bank write bursts +system.physmem.perBankRdBursts::14 18057 # Per bank write bursts +system.physmem.perBankRdBursts::15 18192 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts system.physmem.perBankWrBursts::3 4160 # Per bank write bursts system.physmem.perBankWrBursts::4 4142 # Per bank write bursts system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4262 # Per bank write bursts +system.physmem.perBankWrBursts::6 4261 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4187 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts +system.physmem.perBankWrBursts::9 4180 # Per bank write bursts +system.physmem.perBankWrBursts::10 4148 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,28 +82,28 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 276413976000 # Total gap between requests +system.physmem.totGap 174766169000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292130 # Read request sizes (log2) +system.physmem.readPktSize::6 292166 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 170 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66682 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 215310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,120 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 99419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 230.737062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.797862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.058381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 34339 34.54% 34.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42571 42.82% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9880 9.94% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 767 0.77% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1066 1.07% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 606 0.61% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 182 0.18% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1419 1.43% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8589 8.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 99419 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.841638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.476950 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 763.295063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 96628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.414911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.615169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.362382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31544 32.64% 32.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41851 43.31% 75.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11279 11.67% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 407 0.42% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 349 0.36% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 422 0.44% 88.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 656 0.68% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1511 1.56% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8609 8.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96628 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.731557 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.520071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 729.773377 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.443759 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.423618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.831866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3155 77.82% 77.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 77.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 896 22.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads -system.physmem.totQLat 3656274250 # Total ticks spent queuing -system.physmem.totMemAccLat 9127505500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1458995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12530.11 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.445349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.425120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.833815 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3151 77.74% 77.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 77.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 896 22.11% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 3659606000 # Total ticks spent queuing +system.physmem.totMemAccLat 9131624750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12539.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31280.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 67.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31289.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 24.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 24.42 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.65 # Data bus utilization in percentage -system.physmem.busUtilRead 0.53 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 207034 # Number of row buffer hits during reads -system.physmem.writeRowHits 52000 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 770356.64 # Average gap between requests -system.physmem.pageHitRate 72.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 374197320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204175125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139463000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80208829935 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 95488658250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 195685642110 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.948810 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158328598000 # Time in different power states -system.physmem_0.memoryStateTime::REF 9230000000 # Time in different power states +system.physmem.busUtil 1.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing +system.physmem.readRowHits 209802 # Number of row buffer hits during reads +system.physmem.writeRowHits 52054 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 487020.04 # Average gap between requests +system.physmem.pageHitRate 73.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 364626360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 198952875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139346000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63677219400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 49000374750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 126011580585 # Total energy per rank (pJ) +system.physmem_0.averagePower 721.044153 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81102514500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5835700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108853550750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87824440500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 377342280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 205891125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136187000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80561309670 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 95179465500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 195729613335 # Total energy per rank (pJ) -system.physmem_1.averagePower 708.107889 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 157816922000 # Time in different power states -system.physmem_1.memoryStateTime::REF 9230000000 # Time in different power states +system.physmem_1.actEnergy 365752800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 199567500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136265000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215479440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63630052470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49041749250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 126003495660 # Total energy per rank (pJ) +system.physmem_1.averagePower 720.997890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81165303250 # Time in different power states +system.physmem_1.memoryStateTime::REF 5835700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109365226750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192576024 # Number of BP lookups -system.cpu.branchPred.condPredicted 126054494 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11561226 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 137875105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126274367 # Number of BTB hits +system.cpu.branchPred.lookups 129267026 # Number of BP lookups +system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93510959 # Number of BTB lookups +system.cpu.branchPred.BTBHits 70602364 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.586053 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28678385 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 133 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 75.501700 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19428078 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1137 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14846480 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14819636 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 26844 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 242441427 # DTB read hits -system.cpu.dtb.read_misses 312020 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 242753447 # DTB read accesses -system.cpu.dtb.write_hits 135445847 # DTB write hits -system.cpu.dtb.write_misses 31631 # DTB write misses +system.cpu.dtb.read_hits 243602185 # DTB read hits +system.cpu.dtb.read_misses 267667 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 243869852 # DTB read accesses +system.cpu.dtb.write_hits 101634527 # DTB write hits +system.cpu.dtb.write_misses 39608 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135477478 # DTB write accesses -system.cpu.dtb.data_hits 377887274 # DTB hits -system.cpu.dtb.data_misses 343651 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 378230925 # DTB accesses -system.cpu.itb.fetch_hits 194827904 # ITB hits -system.cpu.itb.fetch_misses 239 # ITB misses +system.cpu.dtb.write_accesses 101674135 # DTB write accesses +system.cpu.dtb.data_hits 345236712 # DTB hits +system.cpu.dtb.data_misses 307275 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 345543987 # DTB accesses +system.cpu.itb.fetch_hits 116217608 # ITB hits +system.cpu.itb.fetch_misses 1594 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 194828143 # ITB accesses +system.cpu.itb.fetch_accesses 116219202 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -320,236 +324,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 552828132 # number of cpu cycles simulated +system.cpu.numCycles 349532518 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 198849781 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1637321417 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192576024 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 154952752 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341932468 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 23591048 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6961 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 194827904 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7885927 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 552584882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963022 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176483 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 116536228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 973715519 # Number of instructions fetch has processed +system.cpu.fetch.Branches 129267026 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 104850078 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 232359516 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 756618 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13025 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 116217608 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 170932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 349287938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.787716 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.090069 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236070631 42.72% 42.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29638226 5.36% 48.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21699661 3.93% 52.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 35773155 6.47% 58.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67709217 12.25% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21596173 3.91% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19328814 3.50% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3978253 0.72% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 116790752 21.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 152570668 43.68% 43.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21852908 6.26% 49.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15618674 4.47% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24569577 7.03% 61.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 38589117 11.05% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15690770 4.49% 76.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12536709 3.59% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3990160 1.14% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 63869355 18.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 552584882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348347 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.961719 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 166809048 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 90546856 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 271205722 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12234440 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11788816 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15468258 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 6932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1567837184 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 24953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11788816 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 173694356 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 60697364 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276538556 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29852032 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1529249378 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8057 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2407484 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 20532473 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7206116 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1021410389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1760087391 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1720201095 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39886295 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 349287938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369828 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.785765 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85729217 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 85771889 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158922951 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18492364 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371517 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11932000 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7014 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 968678626 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25475 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371517 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93246352 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12124008 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14162 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 169252951 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 74278948 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 966798475 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 812 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25198716 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40147884 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7202949 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 666569389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1151537527 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114498375 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 37039151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 382443231 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9068503 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 369184759 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 173801249 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40216404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11112363 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1296784829 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1011355981 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8787623 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 454402873 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 422535596 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 552584882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.830227 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.913668 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27602231 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 87958062 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 245057270 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 102624029 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35348443 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4751860 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 877942600 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 871652294 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 10599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35560646 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10943510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 349287938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.495512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.135180 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197292642 35.70% 35.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90775823 16.43% 52.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 90545836 16.39% 68.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 58767814 10.64% 79.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 57065281 10.33% 89.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29635375 5.36% 94.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 16880319 3.05% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7509205 1.36% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4112587 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75519507 21.62% 21.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 61352705 17.57% 39.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 57497159 16.46% 55.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51075272 14.62% 70.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45041028 12.90% 83.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20641156 5.91% 89.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18147367 5.20% 94.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10284591 2.94% 97.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9729153 2.79% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 552584882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 349287938 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2519786 10.56% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15987276 67.00% 77.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5353537 22.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3589516 19.40% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11788826 63.72% 83.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3123532 16.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 577738940 57.13% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7929 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13232476 1.31% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339799 0.33% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 274563490 27.15% 86.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138645524 13.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 505111201 57.95% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13300877 1.53% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826560 0.44% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339807 0.38% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 244259904 28.02% 88.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 101804815 11.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1011355981 # Type of FU issued -system.cpu.iq.rate 1.829422 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23860599 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023593 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2536933524 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1709848613 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 936642568 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 71011542 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41384153 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34526963 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 998751721 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36463583 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 49725864 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 871652294 # Type of FU issued +system.cpu.iq.rate 2.493766 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18501874 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2041816444 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 876761594 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 835992532 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 69288555 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36778587 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34169821 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 855051836 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35101056 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 65597329 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 131674162 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1208593 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45366 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 75500049 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7546673 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37094 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4322829 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2715 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4217 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4439 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11788816 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59730385 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 188341 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1470365584 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 369184759 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 173801249 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15707 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 184002 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45366 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11555966 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 14467 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11570433 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 973002254 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 242753622 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 38353727 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 371517 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4003286 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 617757 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 966013425 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16652 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 245057270 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 102624029 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 538427 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 92920 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37094 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 15937 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 144140 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 871030251 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 243869972 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 622043 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 173580681 # number of nop insts executed -system.cpu.iew.exec_refs 378231388 # number of memory reference insts executed -system.cpu.iew.exec_branches 128483769 # Number of branches executed -system.cpu.iew.exec_stores 135477766 # Number of stores executed -system.cpu.iew.exec_rate 1.760045 # Inst execution rate -system.cpu.iew.wb_sent 971735602 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 971169531 # cumulative count of insts written-back -system.cpu.iew.wb_producers 554965093 # num instructions producing a value -system.cpu.iew.wb_consumers 830941176 # num instructions consuming a value -system.cpu.iew.wb_rate 1.756730 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667875 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 534547076 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 88070749 # number of nop insts executed +system.cpu.iew.exec_refs 345544428 # number of memory reference insts executed +system.cpu.iew.exec_branches 127159642 # Number of branches executed +system.cpu.iew.exec_stores 101674456 # Number of stores executed +system.cpu.iew.exec_rate 2.491986 # Inst execution rate +system.cpu.iew.wb_sent 870623887 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 870162353 # cumulative count of insts written-back +system.cpu.iew.wb_producers 525000957 # num instructions producing a value +system.cpu.iew.wb_consumers 821946847 # num instructions consuming a value +system.cpu.iew.wb_rate 2.489503 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.638729 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 31811556 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11554519 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 481220935 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.929649 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.612057 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 138434 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345159794 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.690312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.060061 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 204061483 42.40% 42.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 101508829 21.09% 63.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52351815 10.88% 74.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25424424 5.28% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20903892 4.34% 84.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8988981 1.87% 85.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10032197 2.08% 87.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6246270 1.30% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 51703044 10.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109423104 31.70% 31.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 81928646 23.74% 55.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29947333 8.68% 64.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19779535 5.73% 69.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17819278 5.16% 75.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7961935 2.31% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3040960 0.88% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3978860 1.15% 79.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71280143 20.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 481220935 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 345159794 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -595,351 +599,341 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 51703044 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1890031457 # The number of ROB reads -system.cpu.rob.rob_writes 2997634424 # The number of ROB writes -system.cpu.timesIdled 3187 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 243250 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 71280143 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1231657697 # The number of ROB reads +system.cpu.rob.rob_writes 1924928764 # The number of ROB writes +system.cpu.timesIdled 3152 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 244580 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.656268 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.656268 # CPI: Total CPI of All Threads -system.cpu.ipc 1.523768 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.523768 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1234256884 # number of integer regfile reads -system.cpu.int_regfile_writes 703449505 # number of integer regfile writes -system.cpu.fp_regfile_reads 36844868 # number of floating regfile reads -system.cpu.fp_regfile_writes 24462479 # number of floating regfile writes +system.cpu.cpi 0.414933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.414933 # CPI: Total CPI of All Threads +system.cpu.ipc 2.410025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.410025 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1104176449 # number of integer regfile reads +system.cpu.int_regfile_writes 635594518 # number of integer regfile writes +system.cpu.fp_regfile_reads 36406853 # number of floating regfile reads +system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777152 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.896824 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288563683 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 369.362460 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 369982500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.896824 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 776668 # number of replacements +system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780764 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 350.748599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 371412500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4091.068449 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998796 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 582801420 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 582801420 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 191154367 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 191154367 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97409302 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97409302 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 288563669 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 288563669 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 288563669 # number of overall hits -system.cpu.dcache.overall_hits::total 288563669 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554504 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554504 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 891898 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 891898 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2446402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2446402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2446402 # number of overall misses -system.cpu.dcache.overall_misses::total 2446402 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83607056000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83607056000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61973215333 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61973215333 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 82500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 82500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145580271333 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145580271333 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145580271333 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145580271333 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 192708871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 192708871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408623 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 273851866 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 273851866 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 273851866 # number of overall hits +system.cpu.dcache.overall_hits::total 273851866 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554707 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 892577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 892577 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2447284 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2447284 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2447284 # number of overall misses +system.cpu.dcache.overall_misses::total 2447284 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83708553000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83708553000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61914869831 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61914869831 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145623422831 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145623422831 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145623422831 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145623422831 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177997950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177997950 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291010071 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291010071 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 291010071 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 291010071 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008067 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009073 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009073 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.066667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.066667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008407 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008407 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008407 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008407 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53783.750959 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53783.750959 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69484.644357 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69484.644357 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 82500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 82500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59507.910529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59507.910529 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 62248 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 339 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.135693 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 120.402321 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 276299150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 276299150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 276299150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 276299150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008734 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008734 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009080 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009080 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59504.096309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59504.096309 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22333 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 68716 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88616 # number of writebacks -system.cpu.dcache.writebacks::total 88616 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842060 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842060 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823094 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 823094 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1665154 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1665154 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1665154 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1665154 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712444 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712444 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68804 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68804 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781248 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781248 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781248 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781248 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24228621500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24228621500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5666649497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5666649497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29895270997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29895270997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29895270997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29895270997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003697 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003697 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002685 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34007.755697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34007.755697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82359.303195 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82359.303195 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks +system.cpu.dcache.writebacks::total 88604 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842561 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823959 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 823959 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1666520 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1666520 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1666520 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1666520 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712146 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712146 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68618 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68618 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780764 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780764 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780764 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780764 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24226479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24226479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5661245497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5661245497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29887724997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29887724997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4602 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.296070 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 194819661 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6304 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30904.134042 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4617 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6322 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18381.739639 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.296070 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801414 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801414 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1702 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.904441 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1535 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.831055 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 389662112 # Number of tag accesses -system.cpu.icache.tags.data_accesses 389662112 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 194819661 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 194819661 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 194819661 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 194819661 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 194819661 # number of overall hits -system.cpu.icache.overall_hits::total 194819661 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8243 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8243 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8243 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8243 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8243 # number of overall misses -system.cpu.icache.overall_misses::total 8243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 351192999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 351192999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 351192999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 351192999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 351192999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 351192999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 194827904 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 194827904 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 194827904 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 194827904 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 194827904 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 194827904 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42604.998059 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42604.998059 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42604.998059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42604.998059 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 510 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses +system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 116209358 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 116209358 # number of overall hits +system.cpu.icache.overall_hits::total 116209358 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8250 # number of overall misses +system.cpu.icache.overall_misses::total 8250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354158499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354158499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354158499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354158499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354158499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354158499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 116217608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 116217608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 116217608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 116217608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 116217608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 116217608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42928.302909 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42928.302909 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42928.302909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42928.302909 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 738 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.363636 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 4602 # number of writebacks -system.cpu.icache.writebacks::total 4602 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1938 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1938 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1938 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1938 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1938 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1938 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6305 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6305 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6305 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6305 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6305 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6305 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261344999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 261344999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261344999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 261344999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261344999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 261344999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41450.436003 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41450.436003 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41450.436003 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41450.436003 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41450.436003 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41450.436003 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 4617 # number of writebacks +system.cpu.icache.writebacks::total 4617 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1927 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1927 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1927 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1927 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1927 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1927 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6323 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6323 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6323 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6323 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6323 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6323 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 263974500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 263974500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 263974500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 263974500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 263974500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 263974500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41748.299858 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41748.299858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32631.179257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207901 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292487 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.129760 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259794 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292532 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.126188 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2522.721637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 62.286398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30046.171221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001901 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.916936 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2634.083249 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.428877 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29874.113923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.080386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.911686 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994160 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 532 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26438 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 859 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8617 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 22757 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12915747 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12915747 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88616 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88616 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4602 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4602 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2178 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2178 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489639 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 489639 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3605 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491817 # 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number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2700 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289431 # number of overall misses -system.cpu.l2cache.overall_misses::total 292131 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5540303500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5540303500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 213942000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 213942000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18012503500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18012503500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 213942000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23552807000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23766749000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 213942000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23552807000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23766749000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88616 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88616 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4602 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4602 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68804 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68804 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81350.499885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79618.014706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81350.499885 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -948,123 +942,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20656900500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20846271500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.968345 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.968345 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428232 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312733 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312733 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370935 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370935 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73155.277219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73155.277219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69241.481481 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69241.481481 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70844.251700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70844.251700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430176 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.371200 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.371200 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73108.330206 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73108.330206 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69621.691176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69621.691176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70846.047518 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70846.047518 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1569307 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781754 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 1568372 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781285 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1989 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1989 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 718748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68804 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68804 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6305 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712444 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17211 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2356859 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 697984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55671296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56369280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259749 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1047302 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043538 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712146 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338196 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2355458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259794 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1045313 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1989 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1044878 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2003 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1047302 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877871500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9456000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1046881 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877407000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 9483000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171872499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225504 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191079 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225504 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842022 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22964032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadResp 225541 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution +system.membus.trans_dist::CleanEvict 191110 # Transaction distribution +system.membus.trans_dist::ReadExReq 66625 # Transaction distribution +system.membus.trans_dist::ReadExResp 66625 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225541 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842124 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549892 # Request fanout histogram +system.membus.snoop_fanout::samples 549958 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549892 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549958 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549892 # Request fanout histogram -system.membus.reqLayer0.occupancy 880924000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551641250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_fanout::total 549958 # Request fanout histogram +system.membus.reqLayer0.occupancy 877671500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551270000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 5f2d8e18a..35b8ed937 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.542265 # Number of seconds simulated -sim_ticks 542265386500 # Number of ticks simulated -final_tick 542265386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.489946 # Number of seconds simulated +sim_ticks 489945697500 # Number of ticks simulated +final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173269 # Simulator instruction rate (inst/s) -host_op_rate 213317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 146659072 # Simulator tick rate (ticks/s) -host_mem_usage 328008 # Number of bytes of host memory used -host_seconds 3697.46 # Real time elapsed on the host +host_inst_rate 199747 # Simulator instruction rate (inst/s) +host_op_rate 245915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152758149 # Simulator tick rate (ticks/s) +host_mem_usage 280032 # Number of bytes of host memory used +host_seconds 3207.33 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18474304 # Number of bytes read from this memory -system.physmem.bytes_read::total 18637888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory +system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288661 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291217 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291212 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 301668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34068750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34370418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 301668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 301668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7801110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7801110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7801110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 301668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34068750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42171528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291217 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 334143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37705926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38040069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 334143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 334143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8634165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8634165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8634165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 334143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37705926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 46674234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291212 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291217 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291212 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18637888 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18637568 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18283 # Per bank write bursts -system.physmem.perBankRdBursts::1 18129 # Per bank write bursts -system.physmem.perBankRdBursts::2 18220 # Per bank write bursts -system.physmem.perBankRdBursts::3 18184 # Per bank write bursts -system.physmem.perBankRdBursts::4 18283 # Per bank write bursts -system.physmem.perBankRdBursts::5 18405 # Per bank write bursts -system.physmem.perBankRdBursts::6 18181 # Per bank write bursts -system.physmem.perBankRdBursts::7 17993 # Per bank write bursts -system.physmem.perBankRdBursts::8 18030 # Per bank write bursts -system.physmem.perBankRdBursts::9 18058 # Per bank write bursts +system.physmem.perBankRdBursts::0 18282 # Per bank write bursts +system.physmem.perBankRdBursts::1 18130 # Per bank write bursts +system.physmem.perBankRdBursts::2 18217 # Per bank write bursts +system.physmem.perBankRdBursts::3 18178 # Per bank write bursts +system.physmem.perBankRdBursts::4 18288 # Per bank write bursts +system.physmem.perBankRdBursts::5 18411 # Per bank write bursts +system.physmem.perBankRdBursts::6 18177 # Per bank write bursts +system.physmem.perBankRdBursts::7 17990 # Per bank write bursts +system.physmem.perBankRdBursts::8 18028 # Per bank write bursts +system.physmem.perBankRdBursts::9 18056 # Per bank write bursts system.physmem.perBankRdBursts::10 18107 # Per bank write bursts -system.physmem.perBankRdBursts::11 18199 # Per bank write bursts -system.physmem.perBankRdBursts::12 18220 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts +system.physmem.perBankRdBursts::11 18202 # Per bank write bursts +system.physmem.perBankRdBursts::12 18216 # Per bank write bursts +system.physmem.perBankRdBursts::13 18274 # Per bank write bursts system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18260 # Per bank write bursts +system.physmem.perBankRdBursts::15 18258 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4099 # Per bank write bursts system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4223 # Per bank write bursts -system.physmem.perBankWrBursts::5 4222 # Per bank write bursts +system.physmem.perBankWrBursts::4 4225 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542265292000 # Total gap between requests +system.physmem.totGap 489945603000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291217 # Read request sizes (log2) +system.physmem.readPktSize::6 291212 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,95 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111115 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 205.591972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.871353 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.553383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45879 41.29% 41.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43676 39.31% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9414 8.47% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1626 1.46% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 693 0.62% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 670 0.60% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 551 0.50% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8091 7.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111115 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.511200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.259636 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.474106 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 110179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 207.337369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.107709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.005441 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44928 40.78% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43473 39.46% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9308 8.45% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1919 1.74% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 694 0.63% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 753 0.68% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 467 0.42% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 575 0.52% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8062 7.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 110179 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.520538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.272045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.481387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.444749 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.424614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.831636 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3124 77.75% 77.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 77.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 893 22.22% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads -system.physmem.totQLat 2873170250 # Total ticks spent queuing -system.physmem.totMemAccLat 8327545250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9876.83 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.449091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.428808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.834669 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3115 77.55% 77.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 902 22.45% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads +system.physmem.totQLat 3297540750 # Total ticks spent queuing +system.physmem.totMemAccLat 8751747000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11336.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28626.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.80 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30086.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 38.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 38.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.33 # Data bus utilization in percentage -system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.30 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.34 # Average write queue length when enqueuing -system.physmem.readRowHits 194203 # Number of row buffer hits during reads -system.physmem.writeRowHits 51643 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes -system.physmem.avgGap 1517611.33 # Average gap between requests -system.physmem.pageHitRate 68.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 420789600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 229597500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136101200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215537760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107646010785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 230928516000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375994196925 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.386081 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383467912500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18107180000 # Time in different power states +system.physmem.avgWrQLen 22.85 # Average write queue length when enqueuing +system.physmem.readRowHits 195161 # Number of row buffer hits during reads +system.physmem.writeRowHits 51618 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.09 # Row buffer hit rate for writes +system.physmem.avgGap 1371205.96 # Average gap between requests +system.physmem.pageHitRate 69.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 417417840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 227757750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136210400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215563680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 104435392590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 202355359500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 340788331200 # Total energy per rank (pJ) +system.physmem_0.averagePower 695.568361 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 335944764000 # Time in different power states +system.physmem_0.memoryStateTime::REF 16360240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140682990000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 137638069000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 419141520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 228698250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132419600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 107856715275 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230743687500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 376010934465 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.416947 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 383162755000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18107180000 # Time in different power states +system.physmem_1.actEnergy 415474920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 226697625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212608800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 104010891930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ) +system.physmem_1.averagePower 695.442012 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states +system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 140991278500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 154805774 # Number of BP lookups -system.cpu.branchPred.condPredicted 105138294 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90693368 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits +system.cpu.branchPred.lookups 144591747 # Number of BP lookups +system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups +system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.615652 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19277596 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -400,99 +403,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1084530773 # number of cpu cycles simulated +system.cpu.numCycles 979891395 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.692847 # CPI: cycles per instruction -system.cpu.ipc 0.590721 # IPC: instructions per cycle -system.cpu.tickCycles 1025899528 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58631245 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778339 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.484104 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484104 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy +system.cpu.cpi 1.529515 # CPI: cycles per instruction +system.cpu.ipc 0.653802 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction +system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction +system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction +system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 788730744 # Class of committed instruction +system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked +system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778302 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1346 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1585 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759398763 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759398763 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249627706 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249627706 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3486 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3486 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378441471 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378441471 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378444957 # number of overall hits -system.cpu.dcache.overall_hits::total 378444957 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713876 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713876 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 378433272 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378433272 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378436756 # number of overall hits +system.cpu.dcache.overall_hits::total 378436756 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713841 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713841 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 851588 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses -system.cpu.dcache.overall_misses::total 851729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24770851500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24770851500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105356000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105356000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34876207500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34876207500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34876207500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34876207500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 851552 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851552 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851693 # number of overall misses +system.cpu.dcache.overall_misses::total 851693 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25188260500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25188260500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10109820000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10109820000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35298080500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35298080500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35298080500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35298080500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250333347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250333347 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3627 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3627 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379293059 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379293059 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379296686 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379296686 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379284824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379284824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379288449 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379288449 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038875 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038875 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34699.095501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34699.095501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73380.359010 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73380.359010 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40954.320047 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40954.320047 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40947.540239 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40947.540239 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41451.468025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,109 +539,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88693 # number of writebacks -system.cpu.dcache.writebacks::total 88693 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 902 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69292 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69292 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69292 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69292 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712974 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712974 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks +system.cpu.dcache.writebacks::total 88712 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69293 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69293 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712937 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712937 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24041947500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24041947500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067670500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067670500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782259 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782259 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782398 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782398 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24459771500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24459771500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5070040000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5070040000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29109618000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29109618000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29111406000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29111406000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29529811500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29529811500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29531599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29531599500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038324 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038324 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33720.651104 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33720.651104 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73103.351029 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73103.351029 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37210.490658 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37210.490658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37206.165368 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37206.165368 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23591 # number of replacements -system.cpu.icache.tags.tagsinuse 1713.095631 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 291576507 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11505.662813 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 24859 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095631 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 583229042 # Number of tag accesses -system.cpu.icache.tags.data_accesses 583229042 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 291576507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 291576507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 291576507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 291576507 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 291576507 # number of overall hits -system.cpu.icache.overall_hits::total 291576507 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses -system.cpu.icache.overall_misses::total 25343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 498728500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 498728500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 498728500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 498728500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 498728500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 498728500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 291601850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 291601850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 291601850 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 291601850 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 291601850 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 291601850 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19679.142169 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19679.142169 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19679.142169 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19679.142169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19679.142169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19679.142169 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 713113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 25343 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 807778 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 25343 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 807778 # number of overall (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26613 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 26613 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713076 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 713076 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 26613 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782398 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 809011 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 26613 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 809011 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.101093 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.101093 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312148 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312148 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101093 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368961 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360557 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101093 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368961 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360557 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74590.481306 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74590.481306 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76070.062451 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76070.062451 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80061.993198 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80061.993198 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78785.272103 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78785.272103 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096344 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096344 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312155 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312155 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096344 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368970 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.360001 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096344 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368970 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.360001 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -763,115 +801,115 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 27 system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222570 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222570 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288661 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291218 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288661 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291218 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169007000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169007000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15594098500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15594098500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169007000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19862948000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20031955000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169007000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19862948000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20031955000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222563 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222563 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288654 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291213 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288654 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291213 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4271219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4271219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170500500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170500500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16012410500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16012410500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170500500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20283629500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20454130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170500500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20283629500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20454130000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312110 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312110 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360517 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360517 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64590.481306 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64590.481306 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66095.815409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66095.815409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70063.793413 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70063.793413 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096156 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312117 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312117 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359962 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359962 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3351 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 23591 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882361 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343209 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2417485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3131712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 58883904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258813 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1066591 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005113 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.071523 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78084 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2421182 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3294144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55751040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59045184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258808 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1067819 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005072 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.071235 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1061152 99.49% 99.49% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5424 0.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062418 99.49% 99.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5386 0.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1066591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 917138000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225126 # Transaction distribution +system.membus.trans_dist::ReadResp 225121 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190686 # Transaction distribution +system.membus.trans_dist::CleanEvict 190682 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225126 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839218 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839218 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22868160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22867840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22867840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 548001 # Request fanout histogram +system.membus.snoop_fanout::samples 547992 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548001 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 547992 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548001 # Request fanout histogram -system.membus.reqLayer0.occupancy 918049500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 547992 # Request fanout histogram +system.membus.reqLayer0.occupancy 916865000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554665000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554037500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e148c082a..4c772ec0f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.452564 # Number of seconds simulated -sim_ticks 452563515000 # Number of ticks simulated -final_tick 452563515000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.326731 # Number of seconds simulated +sim_ticks 326731324000 # Number of ticks simulated +final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57394 # Simulator instruction rate (inst/s) -host_op_rate 70660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40544083 # Simulator tick rate (ticks/s) -host_mem_usage 306292 # Number of bytes of host memory used -host_seconds 11162.26 # Real time elapsed on the host +host_inst_rate 133673 # Simulator instruction rate (inst/s) +host_op_rate 164569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68173047 # Simulator tick rate (ticks/s) +host_mem_usage 277340 # Number of bytes of host memory used +host_seconds 4792.68 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 234304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48000768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12823616 # Number of bytes read from this memory -system.physmem.bytes_read::total 61058688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 234304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 234304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243456 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200369 # Number of read requests responded to by this memory -system.physmem.num_reads::total 954042 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 106064158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 28335506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134917389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517726 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517726 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9376487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9376487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9376487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 106064158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 28335506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 144293877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 954043 # Number of read requests accepted -system.physmem.writeReqs 66304 # Number of write requests accepted -system.physmem.readBursts 954043 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66304 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61040512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61058752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 53 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory +system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 953240 # Number of read requests accepted +system.physmem.writeReqs 66334 # Number of write requests accepted +system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19632 # Per bank write bursts -system.physmem.perBankRdBursts::1 19241 # Per bank write bursts -system.physmem.perBankRdBursts::2 656774 # Per bank write bursts -system.physmem.perBankRdBursts::3 20103 # Per bank write bursts -system.physmem.perBankRdBursts::4 19565 # Per bank write bursts -system.physmem.perBankRdBursts::5 20788 # Per bank write bursts -system.physmem.perBankRdBursts::6 19429 # Per bank write bursts -system.physmem.perBankRdBursts::7 19781 # Per bank write bursts -system.physmem.perBankRdBursts::8 19292 # Per bank write bursts -system.physmem.perBankRdBursts::9 19805 # Per bank write bursts -system.physmem.perBankRdBursts::10 19337 # Per bank write bursts -system.physmem.perBankRdBursts::11 19452 # Per bank write bursts -system.physmem.perBankRdBursts::12 19407 # Per bank write bursts -system.physmem.perBankRdBursts::13 20952 # Per bank write bursts -system.physmem.perBankRdBursts::14 19359 # Per bank write bursts -system.physmem.perBankRdBursts::15 20841 # Per bank write bursts -system.physmem.perBankWrBursts::0 4254 # Per bank write bursts -system.physmem.perBankWrBursts::1 4107 # Per bank write bursts +system.physmem.perBankRdBursts::0 19685 # Per bank write bursts +system.physmem.perBankRdBursts::1 19287 # Per bank write bursts +system.physmem.perBankRdBursts::2 657567 # Per bank write bursts +system.physmem.perBankRdBursts::3 20052 # Per bank write bursts +system.physmem.perBankRdBursts::4 19480 # Per bank write bursts +system.physmem.perBankRdBursts::5 20770 # Per bank write bursts +system.physmem.perBankRdBursts::6 19386 # Per bank write bursts +system.physmem.perBankRdBursts::7 19760 # Per bank write bursts +system.physmem.perBankRdBursts::8 19321 # Per bank write bursts +system.physmem.perBankRdBursts::9 19768 # Per bank write bursts +system.physmem.perBankRdBursts::10 19303 # Per bank write bursts +system.physmem.perBankRdBursts::11 19444 # Per bank write bursts +system.physmem.perBankRdBursts::12 19433 # Per bank write bursts +system.physmem.perBankRdBursts::13 20871 # Per bank write bursts +system.physmem.perBankRdBursts::14 19269 # Per bank write bursts +system.physmem.perBankRdBursts::15 19527 # Per bank write bursts +system.physmem.perBankWrBursts::0 4288 # Per bank write bursts +system.physmem.perBankWrBursts::1 4110 # Per bank write bursts system.physmem.perBankWrBursts::2 4140 # Per bank write bursts system.physmem.perBankWrBursts::3 4154 # Per bank write bursts -system.physmem.perBankWrBursts::4 4243 # Per bank write bursts -system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.perBankWrBursts::4 4242 # Per bank write bursts +system.physmem.perBankWrBursts::5 4232 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4093 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4155 # Per bank write bursts +system.physmem.perBankWrBursts::15 4146 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 452563504500 # Total gap between requests +system.physmem.totGap 326731313500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 954043 # Read request sizes (log2) +system.physmem.readPktSize::6 953240 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66304 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 760089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 900 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66334 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,47 +148,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -197,112 +197,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 205577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.529062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.622998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.021434 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59787 29.08% 29.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 62582 30.44% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15931 7.75% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3214 1.56% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3392 1.65% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 47997 23.35% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7735 3.76% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 205577 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 209.250931 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.553257 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2756.803776 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 4005 99.40% 99.40% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::61440-65535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::94208-98303 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::114688-118783 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.396271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.276876 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3401 84.41% 84.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.22% 84.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 462 11.47% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 50 1.24% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.89% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.40% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.45% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.25% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.15% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.15% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads -system.physmem.totQLat 15078460254 # Total ticks spent queuing -system.physmem.totMemAccLat 32961422754 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4768790000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15809.52 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads +system.physmem.totQLat 12733277648 # Total ticks spent queuing +system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34559.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 9.37 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.13 # Data bus utilization in percentage -system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 788510 # Number of row buffer hits during reads -system.physmem.writeRowHits 25885 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes -system.physmem.avgGap 443538.82 # Average gap between requests -system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1031660280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 562909875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6203308800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216399600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 305467849845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3582027000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 346623188280 # Total energy per rank (pJ) -system.physmem_0.averagePower 765.915744 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4235605578 # Time in different power states -system.physmem_0.memoryStateTime::REF 15111980000 # Time in different power states +system.physmem.busUtil 1.56 # Data bus utilization in percentage +system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing +system.physmem.readRowHits 805882 # Number of row buffer hits during reads +system.physmem.writeRowHits 26140 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes +system.physmem.avgGap 320458.66 # Average gap between requests +system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) +system.physmem_0.averagePower 771.975754 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states +system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 433212896922 # Time in different power states +system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 522411120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 285045750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1235535600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212738400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96975747585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 186469836000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 315260347335 # Total energy per rank (pJ) -system.physmem_1.averagePower 696.614859 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 309568131397 # Time in different power states -system.physmem_1.memoryStateTime::REF 15111980000 # Time in different power states +system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) +system.physmem_1.averagePower 704.579541 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states +system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127880371103 # Time in different power states +system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234612924 # Number of BP lookups -system.cpu.branchPred.condPredicted 162473080 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514448 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121580360 # Number of BTB lookups -system.cpu.branchPred.BTBHits 107626063 # Number of BTB hits +system.cpu.branchPred.lookups 174663372 # Number of BP lookups +system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.522573 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300027 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,232 +426,232 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 905127031 # number of cpu cycles simulated +system.cpu.numCycles 653462649 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85998683 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1202051079 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234612924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132661709 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 803240111 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064493 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1917 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3269 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370084311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652880 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 904776257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.657297 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222804793 24.63% 24.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 224059137 24.76% 49.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98313262 10.87% 60.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359599065 39.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 904776257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.328047 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121900634 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 244061321 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484657119 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38638613 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518570 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24546046 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13813 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248144936 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968729 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518570 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178911503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 163289745 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 206869 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319515 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82530055 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190655236 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 24276259 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24947259 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2269584 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41529012 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1706231 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1226042317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5813738555 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358185798 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876436 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4376071754 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 351264087 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7264 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108789745 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 367388846 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095095 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1811043 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5312656 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1169837126 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017086167 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18990404 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 381124500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1038523748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 904776257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.124130 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093860 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 248251839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 347117204 38.36% 38.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227104713 25.10% 63.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217802755 24.07% 87.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96630403 10.68% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16121175 1.78% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 904776257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63882217 18.87% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 158029640 46.67% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116058922 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456367665 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322074351 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215594127 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017086167 # Type of FU issued -system.cpu.iq.rate 1.123694 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338625811 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332937 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3234688378 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1507427240 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934273902 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61876428 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565689 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321902233 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9959480 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued +system.cpu.iq.rate 1.316105 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 115147908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114599 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065775 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19869 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518570 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35329075 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27772 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1169855013 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 367388846 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095095 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6592 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 88 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30218 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784620 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221721 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751329 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303296690 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42334838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5555 # number of nop insts executed -system.cpu.iew.exec_refs 497768330 # number of memory reference insts executed -system.cpu.iew.exec_branches 150610966 # Number of branches executed -system.cpu.iew.exec_stores 194471640 # Number of stores executed -system.cpu.iew.exec_rate 1.076922 # Inst execution rate -system.cpu.iew.wb_sent 963724922 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960426352 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536046741 # num instructions producing a value -system.cpu.iew.wb_consumers 893290325 # num instructions consuming a value -system.cpu.iew.wb_rate 1.061096 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600081 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 357426439 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10252 # number of nop insts executed +system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed +system.cpu.iew.exec_branches 143379422 # Number of branches executed +system.cpu.iew.exec_stores 152688943 # Number of stores executed +system.cpu.iew.exec_rate 1.301023 # Inst execution rate +system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487338276 # num instructions producing a value +system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value +system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500772 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 853952830 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.923623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.715196 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 515313788 60.34% 60.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174402011 20.42% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72937800 8.54% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32899590 3.85% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8538808 1.00% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14259214 1.67% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7267758 0.85% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5975049 0.70% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22358812 2.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 853952830 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -692,387 +697,387 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22358812 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1977741776 # The number of ROB reads -system.cpu.rob.rob_writes 2343140199 # The number of ROB writes -system.cpu.timesIdled 648615 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 350774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1500478116 # The number of ROB reads +system.cpu.rob.rob_writes 1798380886 # The number of ROB writes +system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.412828 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.412828 # CPI: Total CPI of All Threads -system.cpu.ipc 0.707800 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.707800 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995808121 # number of integer regfile reads -system.cpu.int_regfile_writes 567906123 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794435958 # number of cc regfile reads -system.cpu.cc_regfile_writes 384896498 # number of cc regfile writes -system.cpu.misc_regfile_reads 715821566 # number of misc regfile reads +system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868460109 # number of integer regfile reads +system.cpu.int_regfile_writes 500697086 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads +system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes +system.cpu.misc_regfile_reads 632347857 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756183 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.937153 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216547 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756695 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258388 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.937153 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756452 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347867 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347867 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906808 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906808 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414200564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414200564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414203721 # number of overall hits -system.cpu.dcache.overall_hits::total 414203721 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3035071 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3035071 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044669 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits +system.cpu.dcache.overall_hits::total 371035352 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4079740 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4079740 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4080386 # number of overall misses -system.cpu.dcache.overall_misses::total 4080386 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76845731000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76845731000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10002174850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10002174850 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86847905850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86847905850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86847905850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86847905850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328827 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses +system.cpu.dcache.overall_misses::total 3447085 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280304 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280304 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284107 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284107 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008101 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.491873 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.491873 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21287.607997 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21284.237778 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 351058 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4882 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.908644 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2756183 # number of writebacks -system.cpu.dcache.writebacks::total 2756183 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999866 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999866 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323646 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks +system.cpu.dcache.writebacks::total 2756452 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1323512 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1323512 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1323512 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1323512 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035205 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756228 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756228 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756869 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756869 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65547149000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 65547149000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5956550350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5956550350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5499000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5499000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71503699350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 71503699350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71509198350 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 71509198350 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8261.248740 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8261.248740 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8578.783151 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8578.783151 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25938.555060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25938.555060 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169029 # number of replacements -system.cpu.icache.tags.tagsinuse 510.720775 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364910405 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169539 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.588578 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.720775 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997502 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997502 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1979880 # number of replacements +system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745338281 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745338281 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364910416 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364910416 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364910416 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364910416 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41967552420 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41967552420 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370084284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370084284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370084284 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370084284 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370084284 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370084284 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013980 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013980 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013980 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367734 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367734 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.095086 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.120377 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 15851796 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925416 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 760180 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116881 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7205559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 7189951 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 987519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8269921 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23778205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661668416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352824192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1014492608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1297843 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9224254 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.222027 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.558758 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7819520 84.77% 84.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 761435 8.25% 93.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 643299 6.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9224254 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15851110000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754813511 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135160937 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 952680 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66304 # Transaction distribution -system.membus.trans_dist::CleanEvict 227429 # Transaction distribution -system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 1362 # Transaction distribution -system.membus.trans_dist::ReadExResp 1362 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 952681 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2201992 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2201992 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65302144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65302144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 951856 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution +system.membus.trans_dist::CleanEvict 227102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 185 # Transaction distribution +system.membus.trans_dist::ReadExReq 1383 # Transaction distribution +system.membus.trans_dist::ReadExResp 1383 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1247950 # Request fanout histogram +system.membus.snoop_fanout::samples 1246861 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1247950 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1247950 # Request fanout histogram -system.membus.reqLayer0.occupancy 1752348040 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 5020538027 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.snoop_fanout::total 1246861 # Request fanout histogram +system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |