diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/long/se/40.perlbmk | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/se/40.perlbmk')
19 files changed, 380 insertions, 128 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 16e2e58d3..c3e480ad3 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index f9974abd8..9147626b9 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:24:16 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 936c3a0e4..b1e9e0d80 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.645508 # Nu sim_ticks 645508416000 # Number of ticks simulated final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101635 # Simulator instruction rate (inst/s) -host_op_rate 101635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35987047 # Simulator tick rate (ticks/s) -host_mem_usage 222212 # Number of bytes of host memory used -host_seconds 17937.24 # Real time elapsed on the host +host_inst_rate 137005 # Simulator instruction rate (inst/s) +host_op_rate 137005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48511232 # Simulator tick rate (ticks/s) +host_mem_usage 222596 # Number of bytes of host memory used +host_seconds 13306.37 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94795136 # Number of bytes read from this memory -system.physmem.bytes_inst_read 192384 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1481174 # Number of read requests responded to by this memory -system.physmem.num_writes 66898 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 146853447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 298035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 6632713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 153486160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 192384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94602752 # Number of bytes read from this memory +system.physmem.bytes_read::total 94795136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 192384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 192384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory +system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1478168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1481174 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 298035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146555412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146853447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 298035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 298035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6632713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6632713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6632713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 298035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146555412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153486160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 402604817 # nu system.cpu.icache.overall_accesses::cpu.inst 402604817 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 402604817 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16625.867453 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16625.867453 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16625.867453 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16625.867453 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 123488000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123488000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 123488000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12139.992135 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12139.992135 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1528059 # number of replacements system.cpu.dcache.tagsinuse 4095.059846 # Cycle average of tags in use @@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 669730731 # nu system.cpu.dcache.overall_accesses::cpu.data 669730731 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 669730731 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002618 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.040000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040000 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003704 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003704 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003704 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003704 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37072.672706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37072.672706 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.941679 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.941679 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37240.290883 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37240.290883 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 99000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked @@ -496,15 +531,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 52483443500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52483443500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 52483443500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.020000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34227.205505 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34227.205505 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34815.073180 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34815.073180 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480784 # number of replacements system.cpu.l2cache.tagsinuse 31940.343129 # Cycle average of tags in use @@ -569,18 +614,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1532155 system.cpu.l2cache.overall_accesses::total 1542327 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.295517 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966291 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.961652 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933607 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933607 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.295517 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.960350 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.960350 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34318.196939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34338.522573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34338.479372 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35134.764398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35134.764398 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34374.418198 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34318.196939 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34374.532529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34374.418198 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 40500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -615,18 +668,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45899201500 system.cpu.l2cache.overall_mshr_miss_latency::total 45992673500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966291 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961652 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933607 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933607 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.960350 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.960350 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31095.143047 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.637348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31000.838210 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32123.320868 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32123.320868 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31051.499351 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31095.143047 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.410597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31051.499351 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index eadae54f6..aa91216e8 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr index ca52b457d..1c6544a2e 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 3888b9787..073913775 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:09 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:31:15 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 271502b93..8a7012f1d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2020056 # Simulator instruction rate (inst/s) -host_op_rate 2020056 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1010246097 # Simulator tick rate (ticks/s) -host_mem_usage 211516 # Number of bytes of host memory used -host_seconds 994.52 # Real time elapsed on the host +host_inst_rate 3539563 # Simulator instruction rate (inst/s) +host_op_rate 3539563 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1770163280 # Simulator tick rate (ticks/s) +host_mem_usage 211940 # Number of bytes of host memory used +host_seconds 567.58 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11607100996 # Number of bytes read from this memory -system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1586125963 # Number of bytes written to this memory -system.physmem.num_reads 2520491096 # Number of read requests responded to by this memory -system.physmem.num_writes 210794896 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11552681087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13131370496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory +system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8037684280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8037684280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1586125963 # Number of bytes written to this memory +system.physmem.bytes_written::total 1586125963 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2009421070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 511070026 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2520491096 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 210794896 # Number of write requests responded to by this memory +system.physmem.num_writes::total 210794896 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3552681501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11552681087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999586 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1578689409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1578689409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 4f0c26637..f9460f41a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index c1dffe98f..508096573 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:40:02 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index df33397d8..c273e38a0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.813468 # Nu sim_ticks 2813467842000 # Number of ticks simulated final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 748813 # Simulator instruction rate (inst/s) -host_op_rate 748813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1048668721 # Simulator tick rate (ticks/s) -host_mem_usage 220468 # Number of bytes of host memory used -host_seconds 2682.89 # Real time elapsed on the host +host_inst_rate 1483350 # Simulator instruction rate (inst/s) +host_op_rate 1483350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2077343480 # Simulator tick rate (ticks/s) +host_mem_usage 220820 # Number of bytes of host memory used +host_seconds 1354.36 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94708160 # Number of bytes read from this memory -system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4281472 # Number of bytes written to this memory -system.physmem.num_reads 1479815 # Number of read requests responded to by this memory -system.physmem.num_writes 66898 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 33662428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 54071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1521777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35184206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94556032 # Number of bytes read from this memory +system.physmem.bytes_read::total 94708160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory +system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1477438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479815 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33608357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33662428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1521777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1521777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1521777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33608357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35184206 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 2009421071 # nu system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23421.857305 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23421.857305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 216390000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 721864922 # nu system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54628.209454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54628.209454 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.273516 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54553.304787 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54553.304787 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 78883980000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78883980000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 78883980000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51628.209454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51628.209454 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1479797 # number of replacements system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use @@ -289,18 +330,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1530144 system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.967338 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.961978 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.965555 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.960457 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.965555 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.960457 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,18 +384,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961978 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.960457 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.960457 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 046ea4974..d9870188c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 5fdff30e2..0c5c10637 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:38:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:06:13 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 25a59d0b1..81f1da57a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.735495 # Nu sim_ticks 735495062500 # Number of ticks simulated final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70506 # Simulator instruction rate (inst/s) -host_op_rate 96019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37458496 # Simulator tick rate (ticks/s) -host_mem_usage 237496 # Number of bytes of host memory used -host_seconds 19634.93 # Real time elapsed on the host +host_inst_rate 76677 # Simulator instruction rate (inst/s) +host_op_rate 104424 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40737062 # Simulator tick rate (ticks/s) +host_mem_usage 237976 # Number of bytes of host memory used +host_seconds 18054.69 # Real time elapsed on the host sim_insts 1384379503 # Number of instructions simulated sim_ops 1885334256 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94839680 # Number of bytes read from this memory -system.physmem.bytes_inst_read 213952 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1481870 # Number of read requests responded to by this memory -system.physmem.num_writes 66099 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 128946726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 290895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5751685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 134698411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory +system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 414743940 # nu system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 192601000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1532415 # number of replacements system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use @@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 1036122172 # nu system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003078 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003078 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 52532835500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001928 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34178.105737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34178.105737 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32230.114990 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32230.114990 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34079.965526 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34079.965526 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480284 # number of replacements system.cpu.l2cache.tagsinuse 31973.508020 # Cycle average of tags in use @@ -584,19 +627,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 1536511 system.cpu.l2cache.overall_accesses::total 1567287 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108786 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964935 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.947305 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999394 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999394 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908791 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.908791 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108786 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.962278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.945519 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108786 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.962278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.945519 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.972521 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34306.089470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34306.025346 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.322034 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.322034 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34296.139278 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.972521 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.178150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34296.139278 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,20 +696,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947286 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999394 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908791 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 3c449c83d..73b2ffcd2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index d0a53e63c..1893c8b1d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:43:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:11:11 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index de6626577..56b9fe676 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.945613 # Nu sim_ticks 945613131000 # Number of ticks simulated final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 910891 # Simulator instruction rate (inst/s) -host_op_rate 1240507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 622191267 # Simulator tick rate (ticks/s) -host_mem_usage 225796 # Number of bytes of host memory used -host_seconds 1519.81 # Real time elapsed on the host +host_inst_rate 1814541 # Simulator instruction rate (inst/s) +host_op_rate 2471154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1239437075 # Simulator tick rate (ticks/s) +host_mem_usage 226248 # Number of bytes of host memory used +host_seconds 762.94 # Real time elapsed on the host sim_insts 1384381614 # Number of instructions simulated sim_ops 1885336367 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8025491315 # Number of bytes read from this memory -system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1123958396 # Number of bytes written to this memory -system.physmem.num_reads 2010616909 # Number of read requests responded to by this memory -system.physmem.num_writes 276945663 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8487076852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 5880931491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1188602780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9675679632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 5561086040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2464405275 # Number of bytes read from this memory +system.physmem.bytes_read::total 8025491315 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5561086040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5561086040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory +system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1390271510 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 620345399 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2010616909 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory +system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5880931491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606145361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8487076852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5880931491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5880931491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188602780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1188602780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5880931491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3794748141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9675679632 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 68de052dd..1dd9a3ff2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index d3e913037..579afd945 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:43:48 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:24:05 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 6675fca21..4610b3f7b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.369902 # Nu sim_ticks 2369901960000 # Number of ticks simulated final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 495417 # Simulator instruction rate (inst/s) -host_op_rate 672068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 849801430 # Simulator tick rate (ticks/s) -host_mem_usage 234976 # Number of bytes of host memory used -host_seconds 2788.77 # Real time elapsed on the host +host_inst_rate 768078 # Simulator instruction rate (inst/s) +host_op_rate 1041952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1317503901 # Simulator tick rate (ticks/s) +host_mem_usage 235416 # Number of bytes of host memory used +host_seconds 1798.78 # Real time elapsed on the host sim_insts 1381604347 # Number of instructions simulated sim_ops 1874244950 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94696320 # Number of bytes read from this memory -system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1479630 # Number of read requests responded to by this memory -system.physmem.num_writes 66099 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39957906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 41742932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94551872 # Number of bytes read from this memory +system.physmem.bytes_read::total 94696320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1477373 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479630 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 60951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39896955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39957906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1785026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1785026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1785026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39896955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41742932 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 1390271511 # nu system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18786.850477 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18786.850477 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18786.850477 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 312627000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15786.850477 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 897271092 # nu system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54574.204602 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54458.738711 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54458.738711 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51574.204602 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1478755 # number of replacements system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1533653 system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.954657 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.952476 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.952476 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59094920000 system.cpu.l2cache.overall_mshr_miss_latency::total 59185200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.954657 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.952476 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.952476 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |