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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
commit4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch)
treec6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/40.perlbmk
parent542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff)
downloadgem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/40.perlbmk')
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini51
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt432
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini17
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout6
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt13
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini50
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout6
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt384
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt475
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini37
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt15
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini72
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout6
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt398
18 files changed, 1222 insertions, 799 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index c87170fbe..2d167e65d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -460,20 +460,13 @@ is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 2a099e16b..af8dce3f0 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:26:04
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:28
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 90210da82..4c98d6289 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.643030 # Nu
sim_ticks 643030478500 # Number of ticks simulated
final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153915 # Simulator instruction rate (inst/s)
-host_tick_rate 54289503 # Simulator tick rate (ticks/s)
-host_mem_usage 215008 # Number of bytes of host memory used
-host_seconds 11844.47 # Real time elapsed on the host
+host_inst_rate 198283 # Simulator instruction rate (inst/s)
+host_op_rate 198283 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69939236 # Simulator tick rate (ticks/s)
+host_mem_usage 217424 # Number of bytes of host memory used
+host_seconds 9194.13 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
+sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94779264 # Number of bytes read from this memory
system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4281472 # Number of bytes written to this memory
@@ -272,6 +274,7 @@ system.cpu.iew.wb_rate 1.604576 # in
system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted
@@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle
-system.cpu.commit.count 2008987604 # Number of instructions committed
+system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
+system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 721864922 # Number of memory references committed
system.cpu.commit.loads 511070026 # Number of loads committed
@@ -308,6 +312,7 @@ system.cpu.rob.rob_writes 6113513811 # Th
system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
+system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads
@@ -325,26 +330,39 @@ system.cpu.icache.total_refs 398299261 # To
system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1650.873085 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.806090 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 398299261 # number of ReadReq hits
-system.cpu.icache.demand_hits 398299261 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 398299261 # number of overall hits
-system.cpu.icache.ReadReq_misses 11100 # number of ReadReq misses
-system.cpu.icache.demand_misses 11100 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 11100 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 182477500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 182477500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 182477500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 398310361 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 398310361 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 398310361 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 16439.414414 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 16439.414414 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 16439.414414 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1650.873085 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.806090 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.806090 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 398299261 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 398299261 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 398299261 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 398299261 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 398299261 # number of overall hits
+system.cpu.icache.overall_hits::total 398299261 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 11100 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 11100 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 11100 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 11100 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 11100 # number of overall misses
+system.cpu.icache.overall_misses::total 11100 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 182477500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 182477500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 182477500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 182477500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 182477500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 182477500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 398310361 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 398310361 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 398310361 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 398310361 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 398310361 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 398310361 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16439.414414 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16439.414414 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 9947 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 9947 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 9947 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 119555000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 119555000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 119555000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000025 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12019.201769 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1153 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1153 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1153 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1153 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1153 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1153 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9947 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 9947 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 9947 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 9947 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 9947 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 9947 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 119555000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 119555000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 119555000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 119555000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 119555000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 119555000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12019.201769 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12019.201769 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1527592 # number of replacements
system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use
@@ -381,38 +402,59 @@ system.cpu.dcache.total_refs 660890207 # To
system.cpu.dcache.sampled_refs 1531688 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 431.478347 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 255376000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4095.113983 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999784 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 450646939 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 210243259 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits 660890198 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 660890198 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1928305 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 551637 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 2479942 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 2479942 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 71444429000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 20878144491 # number of WriteReq miss cycles
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system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
@@ -421,37 +463,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429
system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480630 # number of replacements
system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use
@@ -459,36 +512,75 @@ system.cpu.l2cache.total_refs 63583 # To
system.cpu.l2cache.sampled_refs 1513317 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.042016 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
@@ -497,30 +589,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 66898 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1414071 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 1480926 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 1480926 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 43837380500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147695000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 45985075500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 45985075500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961933 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933664 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.960620 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.960620 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.834117 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.672799 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks
+system.cpu.l2cache.writebacks::total 66898 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2901 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411170 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1414071 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2901 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1478025 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1480926 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2901 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1478025 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1480926 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90197000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43747183500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43837380500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147695000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147695000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90197000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45894878500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 45985075500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90197000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45894878500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 45985075500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966500 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933664 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.692520 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.647335 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32124.672799 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index a895468a4..e114fdc81 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -64,7 +77,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 67c7a90bd..d7926f03a 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:26:36
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:42
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 5a9e50b92..4c63884c7 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 1.004711 # Nu
sim_ticks 1004710587000 # Number of ticks simulated
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4051601 # Simulator instruction rate (inst/s)
-host_tick_rate 2026237516 # Simulator tick rate (ticks/s)
-host_mem_usage 204820 # Number of bytes of host memory used
-host_seconds 495.85 # Real time elapsed on the host
+host_inst_rate 5076159 # Simulator instruction rate (inst/s)
+host_op_rate 5076159 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2538627026 # Simulator tick rate (ticks/s)
+host_mem_usage 206544 # Number of bytes of host memory used
+host_seconds 395.77 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
+sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11607100996 # Number of bytes read from this memory
system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory
system.physmem.bytes_written 1586125963 # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 39 # Nu
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2008987605 # Number of instructions executed
+system.cpu.committedInsts 2008987605 # Number of instructions committed
+system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index f60b78837..794cf18d1 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -130,20 +129,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index e767ec1c4..25b995793 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:28:03
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:14:25
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 668a6f1dd..19236d338 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 2.813468 # Nu
sim_ticks 2813467842000 # Number of ticks simulated
final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1954286 # Simulator instruction rate (inst/s)
-host_tick_rate 2736861040 # Simulator tick rate (ticks/s)
-host_mem_usage 213480 # Number of bytes of host memory used
-host_seconds 1027.99 # Real time elapsed on the host
+host_inst_rate 2306294 # Simulator instruction rate (inst/s)
+host_op_rate 2306294 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3229827855 # Simulator tick rate (ticks/s)
+host_mem_usage 215660 # Number of bytes of host memory used
+host_seconds 871.09 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
+sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94708160 # Number of bytes read from this memory
system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4281472 # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 39 # Nu
system.cpu.numCycles 5626935684 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2008987605 # Number of instructions executed
+system.cpu.committedInsts 2008987605 # Number of instructions committed
+system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
@@ -79,26 +82,39 @@ system.cpu.icache.total_refs 2009410475 # To
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.721886 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
-system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 2009410475 # number of overall hits
-system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
-system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 10596 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1478.423269 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.721886 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.721886 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use
@@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 720334778 # To
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
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@@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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@@ -199,36 +232,75 @@ system.cpu.l2cache.total_refs 63431 # To
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+system.cpu.l2cache.demand_misses::cpu.data 1477438 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1479815 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2377 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1477438 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1479815 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 123604000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73349380000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 73472984000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3477396000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3477396000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 123604000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 76826776000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 76950380000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 123604000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 76826776000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 76950380000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 107612 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 107612 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1530144 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1540740 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.967338 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.965555 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.965555 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -237,30 +309,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 66898 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks
+system.cpu.l2cache.writebacks::total 66898 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410565 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1412942 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1477438 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1479815 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1477438 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1479815 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56422600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56517680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59097520000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 59192600000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 78c85cac9..3a59e4035 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -136,20 +136,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 76bc74d1e..96ddf0fe4 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:06:03
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 801f115d2..b8fd6e344 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.708285 # Nu
sim_ticks 708285420500 # Number of ticks simulated
final_tick 708285420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74841 # Simulator instruction rate (inst/s)
-host_tick_rate 28116271 # Simulator tick rate (ticks/s)
-host_mem_usage 262240 # Number of bytes of host memory used
-host_seconds 25191.30 # Real time elapsed on the host
-sim_insts 1885333786 # Number of instructions simulated
+host_inst_rate 110657 # Simulator instruction rate (inst/s)
+host_op_rate 150700 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56615274 # Simulator tick rate (ticks/s)
+host_mem_usage 229476 # Number of bytes of host memory used
+host_seconds 12510.50 # Real time elapsed on the host
+sim_insts 1384379033 # Number of instructions simulated
+sim_ops 1885333786 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94806144 # Number of bytes read from this memory
system.physmem.bytes_inst_read 201024 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
@@ -281,7 +283,8 @@ system.cpu.iew.wb_penalized 0 # nu
system.cpu.iew.wb_rate 1.741158 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.534869 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1192760864 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 38418907 # The number of times a branch was mispredicted
@@ -302,7 +305,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1198732893 # Number of insts commited each cycle
-system.cpu.commit.count 1885344802 # Number of instructions committed
+system.cpu.commit.committedInsts 1384390049 # Number of instructions committed
+system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908385853 # Number of memory references committed
system.cpu.commit.loads 631388869 # Number of loads committed
@@ -317,12 +321,13 @@ system.cpu.rob.rob_reads 4196573290 # Th
system.cpu.rob.rob_writes 6322749564 # The number of ROB writes
system.cpu.timesIdled 1340847 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51326273 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1885333786 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated
-system.cpu.cpi 0.751363 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.751363 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.330914 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.330914 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 1384379033 # Number of Instructions Simulated
+system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated
+system.cpu.cpi 1.023254 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.023254 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.977275 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.977275 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12567200244 # number of integer regfile reads
system.cpu.int_regfile_writes 2359430733 # number of integer regfile writes
system.cpu.fp_regfile_reads 68800397 # number of floating regfile reads
@@ -335,26 +340,39 @@ system.cpu.icache.total_refs 384162744 # To
system.cpu.icache.sampled_refs 28920 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13283.635685 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1638.335274 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.799968 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 384163979 # number of ReadReq hits
-system.cpu.icache.demand_hits 384163979 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 384163979 # number of overall hits
-system.cpu.icache.ReadReq_misses 34037 # number of ReadReq misses
-system.cpu.icache.demand_misses 34037 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 34037 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 300707500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 300707500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 300707500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 384198016 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 384198016 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 384198016 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 8834.723977 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 8834.723977 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 8834.723977 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1638.335274 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.799968 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.799968 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 384163979 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 384163979 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 384163979 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 384163979 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 384163979 # number of overall hits
+system.cpu.icache.overall_hits::total 384163979 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 34037 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 34037 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 34037 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 34037 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 34037 # number of overall misses
+system.cpu.icache.overall_misses::total 34037 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 300707500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 300707500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 300707500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 300707500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 300707500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 300707500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 384198016 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 384198016 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 384198016 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 384198016 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 384198016 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 384198016 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
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+system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8834.723977 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 775 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses 33262 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses 33262 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 180621500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 180621500 # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency 5430.265769 # average ReadReq mshr miss latency
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-system.cpu.icache.overall_avg_mshr_miss_latency 5430.265769 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 180621500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 180621500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 180621500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 180621500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 180621500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5430.265769 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1531781 # number of replacements
system.cpu.dcache.tagsinuse 4094.791758 # Cycle average of tags in use
@@ -391,40 +412,63 @@ system.cpu.dcache.total_refs 1029515809 # To
system.cpu.dcache.sampled_refs 1535877 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 670.311365 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 305571000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4094.791758 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy
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-system.cpu.dcache.LoadLockedReq_hits 15246 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits
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-system.cpu.dcache.overall_hits 1029475311 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1938073 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 817122 # number of WriteReq misses
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-system.cpu.dcache.ReadReq_miss_latency 69347083500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 28485572000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
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-system.cpu.dcache.ReadReq_accesses 755294828 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 1032230506 # number of demand (read+write) accesses
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-system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.000197 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35781.461018 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 34860.855539 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35508.432434 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35508.432434 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4094.791758 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999705 # Average percentage of cache occupancy
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+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000197 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35781.461018 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34860.855539 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 106815 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 474897 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 740078 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 1214975 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 1214975 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1463176 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 77044 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1540220 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1540220 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 50021914000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 2483063000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 52504977000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 52504977000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34187.216029 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32229.154769 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34089.271013 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34089.271013 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34187.216029 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32229.154769 # average WriteReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34089.271013 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480005 # number of replacements
system.cpu.l2cache.tagsinuse 31970.457215 # Cycle average of tags in use
@@ -467,40 +520,82 @@ system.cpu.l2cache.total_refs 85123 # To
system.cpu.l2cache.sampled_refs 1512725 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.056271 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 29003.484666 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 2966.972548 # Average occupied blocks per context
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-system.cpu.l2cache.ReadReq_accesses 1492097 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 106815 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses 4342 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 72702 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 1564799 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 1564799 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.948525 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate 0.999079 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.908943 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.946686 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.946686 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34308.650659 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.458279 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34298.828182 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34298.828182 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 2966.972548 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 53.821499 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 28949.663167 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.090545 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001643 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.883474 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.975661 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 25776 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 51030 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 76806 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 106815 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 106815 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 6620 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 6620 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 25776 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 57650 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 83426 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 25776 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 57650 # number of overall hits
+system.cpu.l2cache.overall_hits::total 83426 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3145 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1412146 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1415291 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 4338 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 4338 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 66082 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 66082 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3145 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1478228 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1481373 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3145 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1478228 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1481373 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107831000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48448893500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 48556724500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252633500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2252633500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 107831000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 50701527000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 50809358000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 107831000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 50701527000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 50809358000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 28921 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1463176 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1492097 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 106815 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 106815 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4342 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 4342 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 72702 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 72702 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 28921 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1535878 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1564799 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 28921 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1535878 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1564799 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108745 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965124 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999079 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908943 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108745 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.962464 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108745 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.962464 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.486486 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34308.700021 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34088.458279 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -509,35 +604,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 66099 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1415264 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses 4338 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 1481346 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 1481346 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 43971004500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 134478000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 46019602000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 46019602000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948507 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999079 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908943 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.946669 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.946669 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118200 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
+system.cpu.l2cache.writebacks::total 66099 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3141 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412123 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1415264 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4338 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 4338 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66082 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66082 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3141 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1478205 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1481346 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3141 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1478205 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1481346 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97624500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43873380000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43971004500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 134478000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 134478000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048597500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048597500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97624500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45921977500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 46019602000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97624500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45921977500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 46019602000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965108 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999079 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908943 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.706781 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31069.092423 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.839866 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 6a275dc9a..3b0020443 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -88,7 +119,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index dd29e750e..31662be21 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:17:45
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:09:56
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 49ae2817e..a0e247e5f 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.945613 # Nu
sim_ticks 945613131000 # Number of ticks simulated
final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2997522 # Simulator instruction rate (inst/s)
-host_tick_rate 1503443037 # Simulator tick rate (ticks/s)
-host_mem_usage 215364 # Number of bytes of host memory used
-host_seconds 628.97 # Real time elapsed on the host
-sim_insts 1885336367 # Number of instructions simulated
+host_inst_rate 2494982 # Simulator instruction rate (inst/s)
+host_op_rate 3397821 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1704217996 # Simulator tick rate (ticks/s)
+host_mem_usage 217680 # Number of bytes of host memory used
+host_seconds 554.87 # Real time elapsed on the host
+sim_insts 1384381614 # Number of instructions simulated
+sim_ops 1885336367 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8025491315 # Number of bytes read from this memory
system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory
system.physmem.bytes_written 1123958396 # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1411 # Nu
system.cpu.numCycles 1891226263 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1885336367 # Number of instructions executed
+system.cpu.committedInsts 1384381614 # Number of instructions committed
+system.cpu.committedOps 1885336367 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 01aaafc03..62f983a26 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index df0dd80b9..608f1b673 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:28:26
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:19:22
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 117215dc5..70fd39037 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 2.369902 # Nu
sim_ticks 2369901960000 # Number of ticks simulated
final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1407810 # Simulator instruction rate (inst/s)
-host_tick_rate 1780114775 # Simulator tick rate (ticks/s)
-host_mem_usage 224180 # Number of bytes of host memory used
-host_seconds 1331.32 # Real time elapsed on the host
-sim_insts 1874244950 # Number of instructions simulated
+host_inst_rate 1307856 # Simulator instruction rate (inst/s)
+host_op_rate 1774200 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2243399723 # Simulator tick rate (ticks/s)
+host_mem_usage 226844 # Number of bytes of host memory used
+host_seconds 1056.39 # Real time elapsed on the host
+sim_insts 1381604347 # Number of instructions simulated
+sim_ops 1874244950 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94696320 # Number of bytes read from this memory
system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1411 # Nu
system.cpu.numCycles 4739803920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1874244950 # Number of instructions executed
+system.cpu.committedInsts 1381604347 # Number of instructions committed
+system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs 1390251708 # To
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits
-system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1390251708 # number of overall hits
-system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses
-system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 19803 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1390251708 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1390251708 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1390251708 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1390251708 # number of overall hits
+system.cpu.icache.overall_hits::total 1390251708 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses
+system.cpu.icache.overall_misses::total 19803 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 372036000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 372036000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 372036000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1390271511 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1390271511 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1390271511 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312627000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 312627000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312627000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 312627000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1529557 # number of replacements
system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 895757409 # To
system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 895737439 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses
-system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 1533653 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4094.960333 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 618874541 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 618874541 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 895737439 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 895737439 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 895737439 # number of overall hits
+system.cpu.dcache.overall_hits::total 895737439 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
+system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 79725982000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 79725982000 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1478755 # number of replacements
system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 75453 # To
system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------