diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/40.perlbmk | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/40.perlbmk')
8 files changed, 3744 insertions, 3701 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index ef1860117..cf6f894cc 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.190861 # Number of seconds simulated -sim_ticks 1190860634000 # Number of ticks simulated -final_tick 1190860634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.555548 # Number of seconds simulated +sim_ticks 555548307000 # Number of ticks simulated +final_tick 555548307000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304682 # Simulator instruction rate (inst/s) -host_op_rate 304682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180566626 # Simulator tick rate (ticks/s) -host_mem_usage 250024 # Number of bytes of host memory used -host_seconds 6595.13 # Real time elapsed on the host -sim_insts 2009421070 # Number of instructions simulated -sim_ops 2009421070 # Number of ops (including micro ops) simulated +host_inst_rate 201077 # Simulator instruction rate (inst/s) +host_op_rate 201077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120272803 # Simulator tick rate (ticks/s) +host_mem_usage 246132 # Number of bytes of host memory used +host_seconds 4619.07 # Real time elapsed on the host +sim_insts 928789150 # Number of instructions simulated +sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 30476096 # Number of bytes read from this memory -system.physmem.bytes_read::total 30476096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 476189 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25591656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25591656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 156875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3595813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3595813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3595813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25591656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29187469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476189 # Number of read requests accepted -system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476189 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30458432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30476096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 18657152 # Number of bytes read from this memory +system.physmem.bytes_read::total 18657152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 291518 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 33583312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33583312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 336043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 336043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7681982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7681982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7681982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33583312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41265294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291518 # Number of read requests accepted +system.physmem.writeReqs 66683 # Number of write requests accepted +system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18639168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17984 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 281 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29463 # Per bank write bursts -system.physmem.perBankRdBursts::1 29817 # Per bank write bursts -system.physmem.perBankRdBursts::2 29839 # Per bank write bursts -system.physmem.perBankRdBursts::3 29779 # Per bank write bursts -system.physmem.perBankRdBursts::4 29691 # Per bank write bursts -system.physmem.perBankRdBursts::5 29776 # Per bank write bursts -system.physmem.perBankRdBursts::6 29845 # Per bank write bursts -system.physmem.perBankRdBursts::7 29824 # Per bank write bursts -system.physmem.perBankRdBursts::8 29755 # Per bank write bursts -system.physmem.perBankRdBursts::9 29877 # Per bank write bursts -system.physmem.perBankRdBursts::10 29842 # Per bank write bursts -system.physmem.perBankRdBursts::11 29915 # Per bank write bursts -system.physmem.perBankRdBursts::12 29785 # Per bank write bursts -system.physmem.perBankRdBursts::13 29577 # Per bank write bursts -system.physmem.perBankRdBursts::14 29501 # Per bank write bursts -system.physmem.perBankRdBursts::15 29627 # Per bank write bursts +system.physmem.perBankRdBursts::0 17934 # Per bank write bursts +system.physmem.perBankRdBursts::1 18286 # Per bank write bursts +system.physmem.perBankRdBursts::2 18304 # Per bank write bursts +system.physmem.perBankRdBursts::3 18252 # Per bank write bursts +system.physmem.perBankRdBursts::4 18169 # Per bank write bursts +system.physmem.perBankRdBursts::5 18242 # Per bank write bursts +system.physmem.perBankRdBursts::6 18316 # Per bank write bursts +system.physmem.perBankRdBursts::7 18295 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18210 # Per bank write bursts +system.physmem.perBankRdBursts::11 18385 # Per bank write bursts +system.physmem.perBankRdBursts::12 18260 # Per bank write bursts +system.physmem.perBankRdBursts::13 18048 # Per bank write bursts +system.physmem.perBankRdBursts::14 17980 # Per bank write bursts +system.physmem.perBankRdBursts::15 18103 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -69,8 +69,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4222 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -78,23 +78,23 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1190860558500 # Total gap between requests +system.physmem.totGap 555548231500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476189 # Read request sizes (log2) +system.physmem.readPktSize::6 291518 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 475413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 290743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 468 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,110 +189,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 196024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 177.216831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 127.562877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.494740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 75216 38.37% 38.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 90843 46.34% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17447 8.90% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 798 0.41% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 682 0.35% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 656 0.33% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1172 0.60% 95.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1008 0.51% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8202 4.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 196024 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4056 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 115.321252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.815163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1129.679023 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.53% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 7 0.17% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 9 0.22% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-18431 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 104858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.415915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.780585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.040689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39691 37.85% 37.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43831 41.80% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8352 7.97% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1265 1.21% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 732 0.70% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 905 0.86% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1060 1.01% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 884 0.84% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8138 7.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104858 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.322621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.136998 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 770.555291 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4056 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4056 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3063 75.52% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 993 24.48% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4056 # Writes before turning the bus around for reads -system.physmem.totQLat 4642842500 # Total ticks spent queuing -system.physmem.totMemAccLat 13566211250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2379565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9755.65 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458537 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855483 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3076 76.04% 76.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 966 23.88% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads +system.physmem.totQLat 2434432250 # Total ticks spent queuing +system.physmem.totMemAccLat 7895126000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456185000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8358.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28505.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.59 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27108.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.32 # Data bus utilization in percentage +system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 296141 # Number of row buffer hits during reads -system.physmem.writeRowHits 50629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 2192721.67 # Average gap between requests -system.physmem.pageHitRate 63.88 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 589509971750 # Time in different power states -system.physmem.memoryStateTime::REF 39765440000 # Time in different power states +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 202612 # Number of row buffer hits during reads +system.physmem.writeRowHits 50417 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes +system.physmem.avgGap 1550939.92 # Average gap between requests +system.physmem.pageHitRate 70.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275426566250 # Time in different power states +system.physmem.memoryStateTime::REF 18550740000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 561585082000 # Time in different power states +system.physmem.memoryStateTime::ACT 261564123750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 29187469 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409320 # Transaction distribution -system.membus.trans_dist::ReadResp 409320 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66869 # Transaction distribution -system.membus.trans_dist::ReadExResp 66869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019286 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34758208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34758208 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34758208 # Total data (bytes) +system.membus.throughput 41265294 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224874 # Transaction distribution +system.membus.trans_dist::ReadResp 224874 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66644 # Transaction distribution +system.membus.trans_dist::ReadExResp 66644 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22924864 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1283694000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4536921750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.reqLayer0.occupancy 954576500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2724054750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 271010035 # Number of BP lookups -system.cpu.branchPred.condPredicted 174815111 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26224729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 223743631 # Number of BTB lookups -system.cpu.branchPred.BTBHits 179636452 # Number of BTB hits +system.cpu.branchPred.lookups 125108663 # Number of BP lookups +system.cpu.branchPred.condPredicted 80505378 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103330872 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82874855 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.286733 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40316732 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 27614 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18690214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511123125 # DTB read hits -system.cpu.dtb.read_misses 428196 # DTB read misses +system.cpu.dtb.read_hits 237537573 # DTB read hits +system.cpu.dtb.read_misses 198412 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511551321 # DTB read accesses -system.cpu.dtb.write_hits 210802220 # DTB write hits -system.cpu.dtb.write_misses 15121 # DTB write misses +system.cpu.dtb.read_accesses 237735985 # DTB read accesses +system.cpu.dtb.write_hits 98305055 # DTB write hits +system.cpu.dtb.write_misses 7206 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210817341 # DTB write accesses -system.cpu.dtb.data_hits 721925345 # DTB hits -system.cpu.dtb.data_misses 443317 # DTB misses +system.cpu.dtb.write_accesses 98312261 # DTB write accesses +system.cpu.dtb.data_hits 335842628 # DTB hits +system.cpu.dtb.data_misses 205618 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722368662 # DTB accesses -system.cpu.itb.fetch_hits 682230205 # ITB hits +system.cpu.dtb.data_accesses 336048246 # DTB accesses +system.cpu.itb.fetch_hits 315070348 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 682230325 # ITB accesses +system.cpu.itb.fetch_accesses 315070468 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -305,71 +306,72 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 2381721268 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 1111096614 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2009421070 # Number of instructions committed -system.cpu.committedOps 2009421070 # Number of ops (including micro ops) committed -system.cpu.discardedOps 51480727 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 928789150 # Number of instructions committed +system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed +system.cpu.discardedOps 23870770 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.185277 # CPI: cycles per instruction -system.cpu.ipc 0.843684 # IPC: instructions per cycle -system.cpu.tickCycles 2275163827 # Number of cycles that the object actually ticked -system.cpu.idleCycles 106557441 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 20821 # number of replacements -system.cpu.icache.tags.tagsinuse 1689.662119 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 682207641 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 22563 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30235.679697 # Average number of references to valid blocks. +system.cpu.cpi 1.196285 # CPI: cycles per instruction +system.cpu.ipc 0.835921 # IPC: instructions per cycle +system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58548412 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 10608 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.445112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 315057997 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25510.768988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1689.662119 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825030 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825030 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.445112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1364482973 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1364482973 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 682207641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 682207641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 682207641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 682207641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 682207641 # number of overall hits -system.cpu.icache.overall_hits::total 682207641 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 22564 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 22564 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 22564 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 22564 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 22564 # number of overall misses -system.cpu.icache.overall_misses::total 22564 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 467220750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 467220750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 467220750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 467220750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 467220750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 467220750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 682230205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 682230205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 682230205 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 682230205 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 682230205 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 682230205 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20706.468268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20706.468268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20706.468268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20706.468268 # average overall miss latency +system.cpu.icache.tags.tag_accesses 630153046 # Number of tag accesses +system.cpu.icache.tags.data_accesses 630153046 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 315057997 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 315057997 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 315057997 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 315057997 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 315057997 # number of overall hits +system.cpu.icache.overall_hits::total 315057997 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses +system.cpu.icache.overall_misses::total 12351 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 334622500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 334622500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 334622500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 334622500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 334622500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 334622500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 315070348 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 315070348 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 315070348 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 315070348 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 315070348 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 315070348 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27092.745527 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27092.745527 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27092.745527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27092.745527 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,123 +380,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 22564 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 22564 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 22564 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 22564 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 22564 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 22564 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 420842250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 420842250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 420842250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 420842250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 420842250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 420842250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18651.048130 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18651.048130 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308669500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 308669500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308669500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 308669500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308669500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 308669500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24991.458182 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24991.458182 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 88620923 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1481078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1481077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71948 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45127 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156886 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3202013 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1444032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104091136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 105535168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 105535168 # Total data (bytes) +system.cpu.toL2Bus.throughput 101892158 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69010 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56606016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 920456000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 34470750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19151500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371437000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222065750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 443410 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32681.250734 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1100744 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476144 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.311788 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258739 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32601.591220 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 523854 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291475 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.797252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1349.100172 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 31332.150562 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.041171 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956181 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997353 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2678 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29451 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13739996 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13739996 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1071757 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1071757 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95962 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95962 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 5079 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1076836 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1076836 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1076836 # number of overall hits -system.cpu.l2cache.overall_hits::total 1076836 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 409321 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409321 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66869 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66869 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 476190 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476190 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 476190 # number of overall misses -system.cpu.l2cache.overall_misses::total 476190 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29485195750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29485195750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4407101000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4407101000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 33892296750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33892296750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 33892296750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33892296750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1481078 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1481078 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 95962 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 95962 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 71948 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71948 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1553026 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1553026 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1553026 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1553026 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.276367 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.276367 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.929407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.929407 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.306621 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.306621 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.306621 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.306621 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72034.407592 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72034.407592 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65906.488806 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65906.488806 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71173.894349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71173.894349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71173.894349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71173.894349 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 2866.071604 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994922 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2681 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29449 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7436245 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7436245 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 499096 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 499096 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 501462 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 501462 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 501462 # number of overall hits +system.cpu.l2cache.overall_hits::total 501462 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 224875 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66644 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66644 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 291519 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291519 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 291519 # number of overall misses +system.cpu.l2cache.overall_misses::total 291519 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15957253750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15957253750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4332290500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4332290500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20289544250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20289544250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20289544250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20289544250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 723971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 723971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69010 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69010 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 792981 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792981 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792981 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792981 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.310613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.310613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.965715 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965715 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367624 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.367624 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70960.550306 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70960.550306 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65006.459696 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65006.459696 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69599.388891 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69599.388891 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,107 +505,107 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks -system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 409321 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409321 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66869 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66869 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 476190 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476190 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 476190 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476190 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24307408750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24307408750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3543029000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3543029000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27850437750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27850437750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27850437750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27850437750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.276367 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.276367 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.929407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.306621 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.306621 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.306621 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.306621 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59384.709678 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59384.709678 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52984.626658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52984.626658 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58485.977761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58485.977761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58485.977761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58485.977761 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks +system.cpu.l2cache.writebacks::total 66683 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66644 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66644 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 291519 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291519 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 291519 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291519 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13140394750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13140394750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3498793500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3498793500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16639188250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16639188250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16639188250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16639188250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965715 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965715 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367624 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367624 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58434.217899 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58434.217899 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52499.752416 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52499.752416 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1526366 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.558807 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694159033 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1530462 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 453.561757 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 828677250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.558807 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999648 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999648 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 776534 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.879870 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322859768 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 413.588727 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879870 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 948 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1393051346 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1393051346 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 483506411 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 483506411 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 210652622 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210652622 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 694159033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694159033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 694159033 # number of overall hits -system.cpu.dcache.overall_hits::total 694159033 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1459135 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1459135 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 142274 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 142274 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1601409 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1601409 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1601409 # number of overall misses -system.cpu.dcache.overall_misses::total 1601409 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44310462500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44310462500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9194463750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9194463750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 53504926250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53504926250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 53504926250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53504926250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 484965546 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 484965546 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 695760442 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 695760442 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 695760442 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 695760442 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000675 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000675 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002302 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002302 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002302 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002302 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30367.623626 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30367.623626 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64625.045686 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64625.045686 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33411.156207 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33411.156207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33411.156207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33411.156207 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 648198338 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648198338 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 224695721 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224695721 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 322859768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322859768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 322859768 # number of overall hits +system.cpu.dcache.overall_hits::total 322859768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 849086 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses +system.cpu.dcache.overall_misses::total 849086 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22864552750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22864552750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8987445000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8987445000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 31851997750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31851997750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 31851997750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31851997750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 225407654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225407654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 323708854 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323708854 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 323708854 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323708854 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32116.158051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.158051 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65528.606738 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65528.606738 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37513.276335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37513.276335 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,48 +614,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95962 # number of writebacks -system.cpu.dcache.writebacks::total 95962 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 621 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 621 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 70326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 70947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 70947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 70947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 70947 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1458514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 71948 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71948 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1530462 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1530462 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1530462 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1530462 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41263033500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41263033500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529893000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529893000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 45792926500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45792926500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 45792926500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45792926500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28291.146674 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28291.146674 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62960.652138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62960.652138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks +system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 313 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68143 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 68456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69010 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69010 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21363533750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21363533750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4424989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4424989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25788522750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25788522750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30020.985568 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.985568 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64120.982466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64120.982466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c36f62fc3..9bdd841ee 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.635929 # Number of seconds simulated -sim_ticks 635929494500 # Number of ticks simulated -final_tick 635929494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278171 # Number of seconds simulated +sim_ticks 278170874500 # Number of ticks simulated +final_tick 278170874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181383 # Simulator instruction rate (inst/s) -host_op_rate 181383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63271586 # Simulator tick rate (ticks/s) -host_mem_usage 229300 # Number of bytes of host memory used -host_seconds 10050.79 # Real time elapsed on the host -sim_insts 1823043370 # Number of instructions simulated -sim_ops 1823043370 # Number of ops (including micro ops) simulated +host_inst_rate 125961 # Simulator instruction rate (inst/s) +host_op_rate 125961 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41594749 # Simulator tick rate (ticks/s) +host_mem_usage 247184 # Number of bytes of host memory used +host_seconds 6687.64 # Real time elapsed on the host +sim_insts 842382029 # Number of instructions simulated +sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295616 # Number of bytes read from this memory -system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2761 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473369 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 277867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47639898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47917765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 277867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 277867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6733627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6733627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6733627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 277867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47639898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54651392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476130 # Number of read requests accepted -system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476130 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30454144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30472320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 176000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18476352 # Number of bytes read from this memory +system.physmem.bytes_read::total 18652352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288693 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291443 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 632705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66420872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67053576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 632705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 632705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15342052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15342052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15342052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 632705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66420872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82395628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291443 # Number of read requests accepted +system.physmem.writeReqs 66683 # Number of write requests accepted +system.physmem.readBursts 291443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18634688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29443 # Per bank write bursts -system.physmem.perBankRdBursts::1 29787 # Per bank write bursts -system.physmem.perBankRdBursts::2 29841 # Per bank write bursts -system.physmem.perBankRdBursts::3 29778 # Per bank write bursts -system.physmem.perBankRdBursts::4 29678 # Per bank write bursts -system.physmem.perBankRdBursts::5 29749 # Per bank write bursts -system.physmem.perBankRdBursts::6 29855 # Per bank write bursts -system.physmem.perBankRdBursts::7 29842 # Per bank write bursts -system.physmem.perBankRdBursts::8 29764 # Per bank write bursts -system.physmem.perBankRdBursts::9 29879 # Per bank write bursts -system.physmem.perBankRdBursts::10 29841 # Per bank write bursts -system.physmem.perBankRdBursts::11 29912 # Per bank write bursts -system.physmem.perBankRdBursts::12 29773 # Per bank write bursts -system.physmem.perBankRdBursts::13 29578 # Per bank write bursts -system.physmem.perBankRdBursts::14 29495 # Per bank write bursts -system.physmem.perBankRdBursts::15 29631 # Per bank write bursts +system.physmem.perBankRdBursts::0 17914 # Per bank write bursts +system.physmem.perBankRdBursts::1 18261 # Per bank write bursts +system.physmem.perBankRdBursts::2 18310 # Per bank write bursts +system.physmem.perBankRdBursts::3 18245 # Per bank write bursts +system.physmem.perBankRdBursts::4 18158 # Per bank write bursts +system.physmem.perBankRdBursts::5 18234 # Per bank write bursts +system.physmem.perBankRdBursts::6 18318 # Per bank write bursts +system.physmem.perBankRdBursts::7 18307 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::10 18215 # Per bank write bursts +system.physmem.perBankRdBursts::11 18386 # Per bank write bursts +system.physmem.perBankRdBursts::12 18247 # Per bank write bursts +system.physmem.perBankRdBursts::13 18053 # Per bank write bursts +system.physmem.perBankRdBursts::14 17967 # Per bank write bursts +system.physmem.perBankRdBursts::15 18100 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4230 # Per bank write bursts +system.physmem.perBankWrBursts::9 4179 # Per bank write bursts +system.physmem.perBankWrBursts::10 4147 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 635929412000 # Total gap between requests +system.physmem.totGap 278170791500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476130 # Read request sizes (log2) +system.physmem.readPktSize::6 291443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 214189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,112 +193,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 185909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 186.826200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.409449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 215.527814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 65070 35.00% 35.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 87777 47.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 21119 11.36% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 448 0.24% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 430 0.23% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 462 0.25% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 533 0.29% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 575 0.31% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9495 5.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 185909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 100147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 228.644373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.919705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.922323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35701 35.65% 35.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41944 41.88% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10332 10.32% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 643 0.64% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 550 0.55% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 478 0.48% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 606 0.61% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1154 1.15% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8739 8.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100147 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 117.004698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.982691 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1132.774880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4024 99.51% 99.51% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 3 0.07% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 15 0.37% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.435955 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.134261 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 746.811219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.540554 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.517518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.888872 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2948 72.90% 72.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.27% 73.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1080 26.71% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.481701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.460271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.857904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3073 75.99% 75.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 23.86% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 4824243250 # Total ticks spent queuing -system.physmem.totMemAccLat 13746355750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2379230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10138.24 # Average queueing delay per DRAM burst +system.physmem.totQLat 3337058000 # Total ticks spent queuing +system.physmem.totMemAccLat 8796439250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11460.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28888.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30210.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.33 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 306274 # Number of row buffer hits during reads -system.physmem.writeRowHits 50544 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes -system.physmem.avgGap 1171058.77 # Average gap between requests -system.physmem.pageHitRate 65.74 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 176454220250 # Time in different power states -system.physmem.memoryStateTime::REF 21234980000 # Time in different power states +system.physmem.busUtil 0.64 # Data bus utilization in percentage +system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 207319 # Number of row buffer hits during reads +system.physmem.writeRowHits 50340 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.49 # Row buffer hit rate for writes +system.physmem.avgGap 776740.01 # Average gap between requests +system.physmem.pageHitRate 72.00 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 73797472500 # Time in different power states +system.physmem.memoryStateTime::REF 9288500000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 438237480500 # Time in different power states +system.physmem.memoryStateTime::ACT 195078106500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54651392 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409276 # Transaction distribution -system.membus.trans_dist::ReadResp 409276 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66854 # Transaction distribution -system.membus.trans_dist::ReadExResp 66854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019168 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34754432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34754432 # Total data (bytes) +system.membus.throughput 82395628 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224814 # Transaction distribution +system.membus.trans_dist::ReadResp 224814 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66629 # Transaction distribution +system.membus.trans_dist::ReadExResp 66629 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649569 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22920064 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22920064 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1134499000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4452935500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 964230000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2710224500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 402497188 # Number of BP lookups -system.cpu.branchPred.condPredicted 262794086 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25809520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 329924346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 269779526 # Number of BTB hits +system.cpu.branchPred.lookups 192451615 # Number of BP lookups +system.cpu.branchPred.condPredicted 125635967 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11884604 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155866017 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126935891 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.770118 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 58338435 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6772 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.439106 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28844958 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522325129 # DTB read hits -system.cpu.dtb.read_misses 599769 # DTB read misses +system.cpu.dtb.read_hits 244501349 # DTB read hits +system.cpu.dtb.read_misses 309633 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522924898 # DTB read accesses -system.cpu.dtb.write_hits 290323928 # DTB write hits -system.cpu.dtb.write_misses 50170 # DTB write misses +system.cpu.dtb.read_accesses 244810982 # DTB read accesses +system.cpu.dtb.write_hits 135678395 # DTB write hits +system.cpu.dtb.write_misses 31433 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 290374098 # DTB write accesses -system.cpu.dtb.data_hits 812649057 # DTB hits -system.cpu.dtb.data_misses 649939 # DTB misses +system.cpu.dtb.write_accesses 135709828 # DTB write accesses +system.cpu.dtb.data_hits 380179744 # DTB hits +system.cpu.dtb.data_misses 341066 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 813298996 # DTB accesses -system.cpu.itb.fetch_hits 408884134 # ITB hits -system.cpu.itb.fetch_misses 679 # ITB misses +system.cpu.dtb.data_accesses 380520810 # DTB accesses +system.cpu.itb.fetch_hits 196843274 # ITB hits +system.cpu.itb.fetch_misses 340 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 408884813 # ITB accesses +system.cpu.itb.fetch_accesses 196843614 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,507 +310,508 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1271858990 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 556341750 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 427176335 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3374139678 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402497188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 328117961 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 650903682 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 174116050 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 24391105 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7638 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 408884134 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8158289 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1250296288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.698672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.147490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202596472 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648022555 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192451615 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155780849 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341400338 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24237220 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 65 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6944 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 196843274 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6474022 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556122593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176362 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 599392606 47.94% 47.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 59914511 4.79% 52.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43339464 3.47% 56.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 76172685 6.09% 62.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 135820925 10.86% 73.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46245373 3.70% 76.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41570756 3.32% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7626661 0.61% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 240213307 19.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 237070993 42.63% 42.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30141188 5.42% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22117288 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36437929 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67906358 12.21% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21586506 3.88% 74.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299171 3.47% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3525264 0.63% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118037896 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1250296288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.652920 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437590524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 25041136 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 638845250 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1014076 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 147805302 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33122555 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12366 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3318032791 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46593 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 147805302 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 458553010 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7909851 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 618894367 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 17106362 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3208538957 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6484 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17594215 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 887362 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2130246681 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3706452753 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3620701555 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85751197 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 745277611 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4240 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12056800 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 776684532 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 361655801 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 80427234 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13113632 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2720222433 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 90 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2182396478 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17917271 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 897142134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 813907304 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1250296288 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.745503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.834496 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 556122593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345923 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962249 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168349447 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89068138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273848076 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12745104 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12111828 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15365676 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7037 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1585434415 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25396 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12111828 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176490492 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 62059786 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278431125 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27015173 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538086365 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7791 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2366498 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17905765 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6836076 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1026692475 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1767991158 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728209753 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39781404 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 387725317 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1423 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9582425 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372570647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175396988 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40822996 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11172222 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1305164678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1015585029 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462756562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 428157425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 86 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 556122593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.898849 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 456063276 36.48% 36.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196937863 15.75% 52.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 246215948 19.69% 71.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118632312 9.49% 81.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96039549 7.68% 89.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 85322198 6.82% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 31637786 2.53% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19044967 1.52% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 402389 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 196378723 35.31% 35.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93218493 16.76% 52.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 92101634 16.56% 68.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 60001110 10.79% 79.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56881652 10.23% 89.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29459866 5.30% 94.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17057995 3.07% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7198930 1.29% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3824190 0.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1250296288 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556122593 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1147020 2.84% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25333961 62.75% 65.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 13891524 34.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464498 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15571985 66.15% 76.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5503822 23.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1250439249 57.30% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17094 0.00% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851471 1.28% 58.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 592678275 27.16% 86.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 295948284 13.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579410115 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7864 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181855 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276884212 27.26% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138933358 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2182396478 # Type of FU issued -system.cpu.iq.rate 1.715911 # Inst issue rate -system.cpu.iq.fu_busy_cnt 40372505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018499 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5521594502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3528574475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2004997019 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151784518 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88865161 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73949462 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2144972289 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77793942 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63261686 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015585029 # Type of FU issued +system.cpu.iq.rate 1.825470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23540305 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023179 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548815722 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1726656461 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 939949010 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808195 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41310105 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425215 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002762123 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36361935 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50443717 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 265614506 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19945 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 77572 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 150860905 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 135060050 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1143240 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45700 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77095788 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4433 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3083 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2279 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4366 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 147805302 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7602167 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 279549 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3087695808 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 56386 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 776684532 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 361655801 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 90 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 141634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 84137 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 77572 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25803318 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 28659 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25831977 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2081430874 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522925034 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100965604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12111828 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 61105954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191244 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479623370 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16690 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372570647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175396988 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 26783 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 176241 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45700 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11878414 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16350 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11894764 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976099064 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244811165 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39485965 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 367473285 # number of nop insts executed -system.cpu.iew.exec_refs 813299641 # number of memory reference insts executed -system.cpu.iew.exec_branches 277669733 # Number of branches executed -system.cpu.iew.exec_stores 290374607 # Number of stores executed -system.cpu.iew.exec_rate 1.636526 # Inst execution rate -system.cpu.iew.wb_sent 2081298559 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2078946481 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1190563677 # num instructions producing a value -system.cpu.iew.wb_consumers 1779120207 # num instructions consuming a value +system.cpu.iew.exec_nop 174458569 # number of nop insts executed +system.cpu.iew.exec_refs 380521398 # number of memory reference insts executed +system.cpu.iew.exec_branches 129090215 # Number of branches executed +system.cpu.iew.exec_stores 135710233 # Number of stores executed +system.cpu.iew.exec_rate 1.754495 # Inst execution rate +system.cpu.iew.wb_sent 974894086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974374225 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556362190 # num instructions producing a value +system.cpu.iew.wb_consumers 832682807 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.634573 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.669187 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751395 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668156 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1061256381 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25797472 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1102490986 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.822226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.529076 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 543793882 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 11877823 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483108609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.922109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.601347 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 487378417 44.21% 44.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227745323 20.66% 64.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 117618714 10.67% 75.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58023945 5.26% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49786654 4.52% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22711490 2.06% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18023785 1.63% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18535022 1.68% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102667636 9.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205236337 42.48% 42.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102049514 21.12% 63.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51661331 10.69% 74.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25803847 5.34% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21528421 4.46% 84.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9152086 1.89% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10413942 2.16% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6658903 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50604228 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1102490986 # Number of insts commited each cycle -system.cpu.commit.committedInsts 2008987604 # Number of instructions committed -system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 483108609 # Number of insts commited each cycle +system.cpu.commit.committedInsts 928587628 # Number of instructions committed +system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 721864922 # Number of memory references committed -system.cpu.commit.loads 511070026 # Number of loads committed +system.cpu.commit.refs 335811797 # Number of memory references committed +system.cpu.commit.loads 237510597 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 266706457 # Number of branches committed -system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. -system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 185946986 9.26% 9.26% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1058512436 52.69% 61.94% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 15158 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 27517120 1.37% 63.32% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 8254514 0.41% 63.73% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 6876464 0.34% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 4 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 511070026 25.44% 89.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 210794896 10.49% 100.00% # Class of committed instruction +system.cpu.commit.branches 123111018 # Number of branches committed +system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. +system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. +system.cpu.commit.function_calls 18524163 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 2008987604 # Class of committed instruction -system.cpu.commit.bw_lim_events 102667636 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction +system.cpu.commit.bw_lim_events 50604228 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4064430925 # The number of ROB reads -system.cpu.rob.rob_writes 6288295371 # The number of ROB writes -system.cpu.timesIdled 345316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21562702 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1823043370 # Number of Instructions Simulated -system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.697657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.697657 # CPI: Total CPI of All Threads -system.cpu.ipc 1.433369 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.433369 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2650222630 # number of integer regfile reads -system.cpu.int_regfile_writes 1504597172 # number of integer regfile writes -system.cpu.fp_regfile_reads 79149378 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661639 # number of floating regfile writes +system.cpu.rob.rob_reads 1902264753 # The number of ROB reads +system.cpu.rob.rob_writes 3017778261 # The number of ROB writes +system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 219157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 842382029 # Number of Instructions Simulated +system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.660439 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660439 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237156032 # number of integer regfile reads +system.cpu.int_regfile_writes 705771856 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691388 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411317 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 164848262 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470375 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470374 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71643 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159913 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3180016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104188608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104831872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104831872 # Total data (bytes) +system.cpu.toL2Bus.throughput 202299828 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 718925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68836 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12807 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1667041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55864128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56273920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56273920 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914980500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15576999 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 531160500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10099250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2360120750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1208088500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8337 # number of replacements -system.cpu.icache.tags.tagsinuse 1659.365799 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 408871331 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 40679.666799 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4693 # number of replacements +system.cpu.icache.tags.tagsinuse 1650.457565 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 196834917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6403 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30741.045916 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1659.365799 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.810237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.810237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1714 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1650.457565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.805887 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.805887 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1710 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836914 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 817778319 # Number of tag accesses -system.cpu.icache.tags.data_accesses 817778319 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 408871331 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 408871331 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 408871331 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 408871331 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 408871331 # number of overall hits -system.cpu.icache.overall_hits::total 408871331 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12803 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12803 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12803 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12803 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12803 # number of overall misses -system.cpu.icache.overall_misses::total 12803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 381292998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 381292998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 381292998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 381292998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 381292998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 381292998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 408884134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 408884134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 408884134 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 408884134 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 408884134 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 408884134 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000031 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000031 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29781.535421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29781.535421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29781.535421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29781.535421 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834961 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 393692951 # Number of tag accesses +system.cpu.icache.tags.data_accesses 393692951 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 196834917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 196834917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 196834917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 196834917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 196834917 # number of overall hits +system.cpu.icache.overall_hits::total 196834917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8357 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8357 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8357 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8357 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8357 # number of overall misses +system.cpu.icache.overall_misses::total 8357 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329567249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329567249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329567249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329567249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329567249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329567249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 196843274 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 196843274 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 196843274 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 196843274 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 196843274 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 196843274 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39436.071437 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39436.071437 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39436.071437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39436.071437 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2751 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2751 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2751 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2751 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2751 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2751 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10052 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10052 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10052 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10052 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10052 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10052 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281850750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281850750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281850750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281850750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281850750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281850750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28039.270792 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28039.270792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28039.270792 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28039.270792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28039.270792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28039.270792 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1953 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1953 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1953 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1953 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1953 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1953 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6404 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6404 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6404 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6404 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6404 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6404 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242038999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 242038999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242038999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242038999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242038999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242038999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37794.971736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37794.971736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 443352 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32689.433900 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1090130 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476087 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.289771 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258665 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32635.252362 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518921 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291402 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.780774 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1333.307331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 35.512650 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.613920 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040689 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001084 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.955829 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32735 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26895 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998993 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13651722 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13651722 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 7290 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053808 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061098 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95981 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95981 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4789 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7290 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1058597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065887 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7290 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1058597 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065887 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2762 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406515 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409277 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66854 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2762 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 473369 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476131 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2762 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 473369 # number of overall misses -system.cpu.l2cache.overall_misses::total 476131 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198889750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28901614750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29100504500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5230880500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5230880500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 198889750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 34132495250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34331385000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 198889750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 34132495250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34331385000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10052 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460323 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1470375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 95981 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 95981 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71643 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71643 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10052 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1531966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1542018 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10052 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1531966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1542018 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274771 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278373 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.278349 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933155 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.933155 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274771 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.308994 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.308771 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274771 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.308994 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.308771 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72009.322954 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71096.059801 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71102.222944 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78243.343704 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78243.343704 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72009.322954 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72105.472158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72104.914404 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72009.322954 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72105.472158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72104.914404 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 2794.296231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 67.207459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29773.748672 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.085275 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002051 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.908623 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995949 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5318 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26506 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999054 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7394486 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7394486 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 3653 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 490457 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 494110 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91520 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91520 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 2207 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 2207 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3653 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 492664 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 496317 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3653 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 492664 # number of overall hits +system.cpu.l2cache.overall_hits::total 496317 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2751 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 222064 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224815 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66629 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66629 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2751 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288693 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291444 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2751 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288693 # number of overall misses +system.cpu.l2cache.overall_misses::total 291444 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 199081000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16245693500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16444774500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5133040000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5133040000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 199081000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 21378733500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21577814500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 199081000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 21378733500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21577814500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6404 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712521 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 718925 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91520 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91520 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 68836 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 68836 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6404 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 781357 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 787761 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6404 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 781357 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 787761 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.429575 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311660 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.312710 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.967938 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.967938 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.429575 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369476 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.369965 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.429575 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369476 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.369965 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72366.775718 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73157.709039 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73148.030603 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77039.127107 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77039.127107 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72366.775718 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74053.522254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74037.600705 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72366.775718 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74053.522254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74037.600705 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -820,173 +820,173 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks -system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2762 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406515 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409277 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2762 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473369 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476131 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2762 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473369 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476131 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164041750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23797651250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23961693000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4425694500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4425694500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164041750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28223345750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28387387500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164041750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28223345750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28387387500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278373 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278349 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933155 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933155 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308994 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308771 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274771 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308994 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308771 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59392.378711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58540.647332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58546.395229 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66199.397194 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66199.397194 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59392.378711 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59622.294130 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59620.960408 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59392.378711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59622.294130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59620.960408 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks +system.cpu.l2cache.writebacks::total 66683 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2751 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224815 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66629 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66629 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288693 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291444 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2751 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288693 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291444 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164368500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13475868000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13640236500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4316476500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4316476500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17792344500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17956713000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17792344500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17956713000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.429575 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311660 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967938 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967938 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429575 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.369965 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429575 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.369965 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59748.636859 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60684.613445 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60673.160154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64783.750319 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64783.750319 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59748.636859 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61630.675146 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61612.910199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59748.636859 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61630.675146 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61612.910199 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527870 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.609891 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 666862520 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531966 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 435.298512 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 407274250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.609891 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999661 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999661 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777261 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.039148 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289853249 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781357 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 370.961352 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.039148 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2348 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2496 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1341234178 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1341234178 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 457128371 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457128371 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209734126 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209734126 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 666862497 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 666862497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 666862497 # number of overall hits -system.cpu.dcache.overall_hits::total 666862497 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1927816 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1927816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1060770 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1060770 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2988586 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2988586 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2988586 # number of overall misses -system.cpu.dcache.overall_misses::total 2988586 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76893359750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76893359750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 46482150765 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 46482150765 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 123375510515 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 123375510515 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 123375510515 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 123375510515 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 459056187 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 459056187 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 23 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 23 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 669851083 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 669851083 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 669851083 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 669851083 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004200 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004200 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005032 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005032 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004462 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004462 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004462 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004462 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39886.254575 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39886.254575 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43819.254659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43819.254659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41282.235316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41282.235316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41282.235316 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19699 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 140 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 433 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.494226 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 140 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 585486507 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585486507 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192472293 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192472293 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97380937 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97380937 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 19 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 19 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289853230 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289853230 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289853230 # number of overall hits +system.cpu.dcache.overall_hits::total 289853230 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1579063 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1579063 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 920263 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 920263 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2499326 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2499326 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2499326 # number of overall misses +system.cpu.dcache.overall_misses::total 2499326 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79789190750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79789190750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377622714 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57377622714 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137166813464 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137166813464 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137166813464 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137166813464 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194051356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194051356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 19 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292352556 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292352556 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292352556 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292352556 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008137 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008137 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009362 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009362 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008549 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008549 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008549 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008549 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50529.453701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50529.453701 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62349.157484 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62349.157484 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54881.521444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54881.521444 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 55443 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 471 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.690021 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107.447674 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95981 # number of writebacks -system.cpu.dcache.writebacks::total 95981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467493 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467493 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 989127 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 989127 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1456620 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1456620 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1456620 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1456620 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460323 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460323 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531966 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531966 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531966 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531966 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40901282750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40901282750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5350796500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5350796500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46252079250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46252079250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46252079250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46252079250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002287 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002287 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28008.380851 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28008.380851 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74686.940804 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74686.940804 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91520 # number of writebacks +system.cpu.dcache.writebacks::total 91520 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 866542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851427 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 851427 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1717969 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1717969 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1717969 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1717969 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712521 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712521 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68836 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68836 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781357 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781357 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781357 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781357 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21863154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21863154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5224164248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5224164248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27087318248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27087318248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27087318248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27087318248 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002673 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30684.224044 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30684.224044 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75892.908478 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75892.908478 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 6bfc9d3ce..2d72b8ec8 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.004711 # Number of seconds simulated -sim_ticks 1004710587000 # Number of ticks simulated -final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.464395 # Number of seconds simulated +sim_ticks 464394627000 # Number of ticks simulated +final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2670371 # Simulator instruction rate (inst/s) -host_op_rate 2670371 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1335473702 # Simulator tick rate (ticks/s) -host_mem_usage 265688 # Number of bytes of host memory used -host_seconds 752.33 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -sim_ops 2008987605 # Number of ops (including micro ops) simulated +host_inst_rate 1843860 # Simulator instruction rate (inst/s) +host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 922130037 # Simulator tick rate (ticks/s) +host_mem_usage 234352 # Number of bytes of host memory used +host_seconds 503.61 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory -system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1586125963 # Number of bytes written to this memory -system.physmem.bytes_written::total 1586125963 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2009421070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 511070026 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2520491096 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 210794896 # Number of write requests responded to by this memory -system.physmem.num_writes::total 210794896 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3552681501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11552681087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13131370496 # Throughput (bytes/s) -system.membus.data_through_bus 13193226959 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory +system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory +system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13156831461 # Throughput (bytes/s) +system.membus.data_through_bus 6109961839 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.data_hits 721864922 # DTB hits -system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722298387 # DTB accesses -system.cpu.itb.fetch_hits 2009421070 # ITB hits +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789150 # ITB hits system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2009421175 # ITB accesses +system.cpu.itb.fetch_accesses 928789255 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -71,64 +71,64 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 2009421175 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 928789255 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2008987605 # Number of instructions committed -system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses -system.cpu.num_func_calls 79910682 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls -system.cpu.num_int_insts 1779374816 # number of integer instructions -system.cpu.num_fp_insts 71831671 # number of float instructions -system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read -system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written -system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read -system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written -system.cpu.num_mem_refs 722298387 # number of memory refs -system.cpu.num_load_insts 511488910 # Number of load instructions -system.cpu.num_store_insts 210809477 # Number of store instructions +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2009421175 # Number of busy cycles +system.cpu.num_busy_cycles 928789255 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 266706457 # Number of branches fetched -system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction -system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction -system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction -system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction -system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2009421070 # Class of executed instruction +system.cpu.op_class::total 928789150 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index ef8e8a3ca..9f0d0f3c5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.769740 # Number of seconds simulated -sim_ticks 2769739533000 # Number of ticks simulated -final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.286250 # Number of seconds simulated +sim_ticks 1286249820000 # Number of ticks simulated +final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1094265 # Simulator instruction rate (inst/s) -host_op_rate 1094265 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1508635104 # Simulator tick rate (ticks/s) -host_mem_usage 274392 # Number of bytes of host memory used -host_seconds 1835.92 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -sim_ops 2008987605 # Number of ops (including micro ops) simulated +host_inst_rate 839019 # Simulator instruction rate (inst/s) +host_op_rate 839019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162182391 # Simulator tick rate (ticks/s) +host_mem_usage 244120 # Number of bytes of host memory used +host_seconds 1106.75 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory -system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory +system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12529860 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408476 # Transaction distribution -system.membus.trans_dist::ReadResp 408476 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66873 # Transaction distribution -system.membus.trans_dist::ReadExResp 66873 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1017606 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1017606 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34704448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34704448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34704448 # Total data (bytes) +system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 17781280 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22871168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.data_hits 721864922 # DTB hits -system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722298387 # DTB accesses -system.cpu.itb.fetch_hits 2009421071 # ITB hits +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789151 # ITB hits system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2009421176 # ITB accesses +system.cpu.itb.fetch_accesses 928789256 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -85,118 +85,118 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5539479066 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 2572499640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2008987605 # Number of instructions committed -system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses -system.cpu.num_func_calls 79910682 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls -system.cpu.num_int_insts 1779374816 # number of integer instructions -system.cpu.num_fp_insts 71831671 # number of float instructions -system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read -system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written -system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read -system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written -system.cpu.num_mem_refs 722298387 # number of memory refs -system.cpu.num_load_insts 511488910 # Number of load instructions -system.cpu.num_store_insts 210809477 # Number of store instructions +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5539479066 # Number of busy cycles +system.cpu.num_busy_cycles 2572499640 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 266706457 # Number of branches fetched -system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction -system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction -system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction -system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction -system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2009421070 # Class of executed instruction -system.cpu.icache.tags.replacements 9046 # number of replacements -system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.icache.tags.replacements 4618 # number of replacements +system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4018852738 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4018852738 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits -system.cpu.icache.overall_hits::total 2009410475 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10596 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses -system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2009421071 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits +system.cpu.icache.overall_hits::total 928782983 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses +system.cpu.icache.overall_misses::total 6168 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,123 +205,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10596 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442570 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257900 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32732 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31199 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998901 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13642206 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13642206 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96129 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96129 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8443 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1056948 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065391 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8443 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1056948 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065391 # number of overall hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7386496 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7386496 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 4015 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 489636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 493651 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91660 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91660 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4015 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 492002 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 496017 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4015 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 492002 # number of overall hits +system.cpu.l2cache.overall_hits::total 496017 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2153 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406323 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408476 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66873 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66873 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 221878 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224031 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 473196 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475349 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288526 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290679 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 473196 # number of overall misses -system.cpu.l2cache.overall_misses::total 475349 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses +system.cpu.l2cache.overall_misses::total 290679 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21128799000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21240755000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3477396000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3477396000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11537659000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11649615000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3465696000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3465696000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24606195000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24718151000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15003355000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15115311000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24606195000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24718151000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1530144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.203190 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278648 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.278104 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203190 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.309249 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.308520 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203190 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.309249 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.308520 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_latency::cpu.data 15003355000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15115311000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311839 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.312159 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369655 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.369493 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.007383 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.007344 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.006311 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.006311 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -330,119 +330,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks -system.cpu.l2cache.writebacks::total 66908 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks +system.cpu.l2cache.writebacks::total 66683 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406323 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408476 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221878 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224031 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473196 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290679 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473196 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475349 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16252923000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16339043000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8875123000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8961243000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2665920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2665920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18927843000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19013963000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11541043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11627163000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18927843000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19013963000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278648 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308520 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308520 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11541043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11627163000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1526048 # number of replacements -system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 776432 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 999 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1445259988 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1445259988 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits -system.cpu.dcache.overall_hits::total 720334778 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses -system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits +system.cpu.dcache.overall_hits::total 335031269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses +system.cpu.dcache.overall_misses::total 780528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,60 +451,60 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks -system.cpu.dcache.writebacks::total 96129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks +system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 678144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104081472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104759616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes) +system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 3a1bb990b..dc7a25182 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,597 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1252658454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 126529 # Simulator instruction rate (inst/s) -host_mem_usage 303852 # Number of bytes of host memory used -host_op_rate 172315 # Simulator op (including micro ops) rate (op/s) -host_seconds 10941.24 # Real time elapsed on the host -host_tick_rate 114489637 # Simulator tick rate (ticks/s) +sim_seconds 0.537826 # Number of seconds simulated +sim_ticks 537826498500 # Number of ticks simulated +final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1384383018 # Number of instructions simulated -sim_ops 1885337770 # Number of ops (including micro ops) simulated -sim_seconds 1.252658 # Number of seconds simulated -sim_ticks 1252658454500 # Number of ticks simulated +host_inst_rate 114564 # Simulator instruction rate (inst/s) +host_op_rate 141043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96175687 # Simulator tick rate (ticks/s) +host_mem_usage 263048 # Number of bytes of host memory used +host_seconds 5592.13 # Real time elapsed on the host +sim_insts 640655084 # Number of instructions simulated +sim_ops 788730743 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.275361 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 183176705 # Number of BTB hits -system.cpu.branchPred.BTBLookups 198510960 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 2809 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 27775706 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 271023918 # Number of conditional branches predicted -system.cpu.branchPred.lookups 347774230 # Number of BP lookups -system.cpu.branchPred.usedRAS 40383236 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 1384383018 # Number of instructions committed -system.cpu.committedOps 1885337770 # Number of ops (including micro ops) committed -system.cpu.cpi 1.809699 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 9985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 622157845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 622157845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30504.122168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30504.122168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28441.732178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28441.732178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 620694666 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 620694666 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44632990969 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44632990969 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002352 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002352 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 1463179 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1463179 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 1721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41566397026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41566397026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1461458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1461458 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64418.412606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64418.412606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62661.295309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62661.295309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 276792059 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276792059 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9251708000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9251708000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 143619 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143619 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 70841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4560363750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4560363750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 72778 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72778 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 899093523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 899093523 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33535.453099 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 897486725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 897486725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 53884698969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53884698969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.001787 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001787 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 1606798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1606798 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 72562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 46126760776 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46126760776 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001706 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1534236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534236 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 899093523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 899093523 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33535.453099 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 897486725 # number of overall hits -system.cpu.dcache.overall_hits::total 897486725 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 53884698969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53884698969 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.001787 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001787 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 1606798 # number of overall misses -system.cpu.dcache.overall_misses::total 1606798 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 72562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 46126760776 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46126760776 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001706 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1534236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534236 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1240 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1699 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 584.986075 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1799761222 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.531713 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999642 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999642 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1530140 # number of replacements -system.cpu.dcache.tags.sampled_refs 1534236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1799761222 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4094.531713 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 897506695 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 756574250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 96100 # number of writebacks -system.cpu.dcache.writebacks::total 96100 # number of writebacks -system.cpu.discardedOps 58655042 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 655834828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 655834828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15794.863845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15794.863845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13774.677486 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13774.677486 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 655779494 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 655779494 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 873992996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 873992996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 55334 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 55334 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 762208004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 762208004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 55334 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 55334 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 655834828 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 655834828 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15794.863845 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 655779494 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 655779494 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 873992996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 873992996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 55334 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 55334 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 762208004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 762208004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 55334 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 55334 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 655834828 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 655834828 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15794.863845 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 655779494 # number of overall hits -system.cpu.icache.overall_hits::total 655779494 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 873992996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 873992996 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 55334 # number of overall misses -system.cpu.icache.overall_misses::total 55334 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 762208004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 762208004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 55334 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 55334 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 11851.508033 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 1311724989 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1727.262157 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.843390 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.843390 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1765 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.861816 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 53568 # number of replacements -system.cpu.icache.tags.sampled_refs 55333 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 1311724989 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1727.262157 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 655779494 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 103571975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.552578 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 72778 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72778 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66889.147375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66889.147375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54354.270691 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54354.270691 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 6688 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6688 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4420703750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4420703750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.908104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.908104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3592273750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3592273750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.908104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1516792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1516792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72703.861690 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72703.861690 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60134.219047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60134.219047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 1107826 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1107826 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29733407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29733407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.269626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 408966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 30 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24591047000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24591047000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 408936 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408936 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 96100 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96100 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 96100 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96100 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 1589570 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1589570 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71894.916073 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1114514 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1114514 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 34154111250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34154111250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.298858 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.298858 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 475056 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475056 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28183320750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28183320750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.298839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 475026 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475026 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 1589570 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1589570 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71894.916073 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1114514 # number of overall hits -system.cpu.l2cache.overall_hits::total 1114514 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 34154111250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34154111250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.298858 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.298858 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 475056 # number of overall misses -system.cpu.l2cache.overall_misses::total 475056 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28183320750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28183320750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.298839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 475026 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475026 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2580 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29670 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 2.395162 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 14033128 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 1330.818076 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 31344.832788 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040613 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997182 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 442246 # number of replacements -system.cpu.l2cache.tags.sampled_refs 474990 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 14033128 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 32675.650864 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1137678 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks -system.cpu.l2cache.writebacks::total 66099 # number of writebacks -system.cpu.numCycles 2505316909 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 2401744934 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 107882816 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 110667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3164572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3275239 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 938935000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 83558996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2375968224 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 86123089 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3541312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104341504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 107882816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 1516792 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1516791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72778 # Transaction distribution -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 34631936 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1016149 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1016149 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1205459500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4468586250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 27646751 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34631936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34631936 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 408935 # Transaction distribution -system.membus.trans_dist::ReadResp 408935 # Transaction distribution -system.membus.trans_dist::Writeback 66099 # Transaction distribution -system.membus.trans_dist::ReadExReq 66090 # Transaction distribution -system.membus.trans_dist::ReadExResp 66090 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 2314919.25 # Average gap between requests -system.physmem.avgMemAccLat 29362.18 # Average memory access latency per DRAM burst -system.physmem.avgQLat 10612.18 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 24.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 24.27 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.38 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 26.46 # Average write queue length when enqueuing -system.physmem.busUtil 0.22 # Data bus utilization in percentage -system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 133348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 133348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 24269664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 24269664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3377087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 24269664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 27646751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 3377087 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3377087 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 204371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 169.307779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 122.893449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.869772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 84097 41.15% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 91184 44.62% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16888 8.26% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 803 0.39% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1089 0.53% 94.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1331 0.65% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 576 0.28% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 520 0.25% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7883 3.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 204371 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 30374976 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 30401600 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 26624 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 4230336 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 30401600 # Number of bytes read from this memory -system.physmem.bytes_read::total 30401600 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 639262116250 # Time in different power states -system.physmem.memoryStateTime::REF 41828800000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 571561257500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory +system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290531 # Number of read requests accepted +system.physmem.writeReqs 66098 # Number of write requests accepted +system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 475025 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475025 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.pageHitRate 62.20 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 29837 # Per bank write bursts -system.physmem.perBankRdBursts::1 29647 # Per bank write bursts -system.physmem.perBankRdBursts::2 29757 # Per bank write bursts -system.physmem.perBankRdBursts::3 29702 # Per bank write bursts -system.physmem.perBankRdBursts::4 29776 # Per bank write bursts -system.physmem.perBankRdBursts::5 29847 # Per bank write bursts -system.physmem.perBankRdBursts::6 29613 # Per bank write bursts -system.physmem.perBankRdBursts::7 29430 # Per bank write bursts -system.physmem.perBankRdBursts::8 29457 # Per bank write bursts -system.physmem.perBankRdBursts::9 29488 # Per bank write bursts -system.physmem.perBankRdBursts::10 29541 # Per bank write bursts -system.physmem.perBankRdBursts::11 29643 # Per bank write bursts -system.physmem.perBankRdBursts::12 29678 # Per bank write bursts -system.physmem.perBankRdBursts::13 29796 # Per bank write bursts -system.physmem.perBankRdBursts::14 29601 # Per bank write bursts -system.physmem.perBankRdBursts::15 29796 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts -system.physmem.perBankWrBursts::1 4100 # Per bank write bursts +system.physmem.perBankRdBursts::0 18283 # Per bank write bursts +system.physmem.perBankRdBursts::1 18133 # Per bank write bursts +system.physmem.perBankRdBursts::2 18223 # Per bank write bursts +system.physmem.perBankRdBursts::3 18187 # Per bank write bursts +system.physmem.perBankRdBursts::4 18258 # Per bank write bursts +system.physmem.perBankRdBursts::5 18313 # Per bank write bursts +system.physmem.perBankRdBursts::6 18090 # Per bank write bursts +system.physmem.perBankRdBursts::7 17910 # Per bank write bursts +system.physmem.perBankRdBursts::8 17943 # Per bank write bursts +system.physmem.perBankRdBursts::9 17966 # Per bank write bursts +system.physmem.perBankRdBursts::10 18023 # Per bank write bursts +system.physmem.perBankRdBursts::11 18118 # Per bank write bursts +system.physmem.perBankRdBursts::12 18159 # Per bank write bursts +system.physmem.perBankRdBursts::13 18277 # Per bank write bursts +system.physmem.perBankRdBursts::14 18081 # Per bank write bursts +system.physmem.perBankRdBursts::15 18260 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts +system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts +system.physmem.perBankWrBursts::3 4147 # Per bank write bursts +system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::10 4094 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4094 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.067006 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 508.980201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 474221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 537826410500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 290531 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66098 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -621,30 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 475025 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 475025 # Read request sizes (log2) -system.physmem.readReqs 475025 # Number of read requests accepted -system.physmem.readRowHitRate 60.31 # Row buffer hit rate for reads -system.physmem.readRowHits 286253 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 416 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 2373045000 # Total ticks spent in databus transfers -system.physmem.totGap 1252658366500 # Total gap between requests -system.physmem.totMemAccLat 13935557250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 5036638500 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489144 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.467620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859483 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3026 75.52% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2 0.05% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -660,8 +140,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see @@ -672,12 +152,12 @@ system.physmem.wrQLenPdf::23 4008 # Wh system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -709,17 +189,537 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 66099 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66099 # Write request sizes (log2) -system.physmem.writeReqs 66099 # Number of write requests accepted -system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes -system.physmem.writeRowHits 50044 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads +system.physmem.totQLat 3341298000 # Total ticks spent queuing +system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.33 # Data bus utilization in percentage +system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing +system.physmem.readRowHits 194846 # Number of row buffer hits during reads +system.physmem.writeRowHits 49995 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgGap 1508083.78 # Average gap between requests +system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states +system.physmem.memoryStateTime::REF 17958980000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 42437954 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224439 # Transaction distribution +system.membus.trans_dist::ReadResp 224439 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66092 # Transaction distribution +system.membus.trans_dist::ReadExResp 66092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22824256 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 154837020 # Number of BP lookups +system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 1075652997 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 640655084 # Number of instructions committed +system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed +system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.678989 # CPI: cycles per instruction +system.cpu.ipc 0.595596 # IPC: instructions per cycle +system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked +system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 23597 # number of replacements +system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses +system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits +system.cpu.icache.overall_hits::total 289999264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses +system.cpu.icache.overall_misses::total 25348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 257750 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2831 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29389 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7553321 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7553321 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 513976 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 513976 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 517207 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517207 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 517207 # number of overall hits +system.cpu.l2cache.overall_hits::total 517207 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 224469 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224469 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66092 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 290561 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses +system.cpu.l2cache.overall_misses::total 290561 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 807768 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 807768 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 807768 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.303975 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.303975 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953392 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953392 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks +system.cpu.l2cache.writebacks::total 66098 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 29 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 29 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224440 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66092 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66092 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953392 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 778324 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378453595 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782420 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.696218 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 745524250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.650508 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1354 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1577 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759392478 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759392478 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 249628224 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249628224 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 128813893 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813893 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 378442117 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378442117 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 378442117 # number of overall hits +system.cpu.dcache.overall_hits::total 378442117 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 713850 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137584 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137584 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 851434 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses +system.cpu.dcache.overall_misses::total 851434 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks +system.cpu.dcache.writebacks::total 91420 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index fbd52f02a..e42758d84 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.634728 # Number of seconds simulated -sim_ticks 634728078000 # Number of ticks simulated -final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.297198 # Number of seconds simulated +sim_ticks 297198275500 # Number of ticks simulated +final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97161 # Simulator instruction rate (inst/s) -host_op_rate 132320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44547849 # Simulator tick rate (ticks/s) -host_mem_usage 267228 # Number of bytes of host memory used -host_seconds 14248.23 # Real time elapsed on the host -sim_insts 1384370590 # Number of instructions simulated -sim_ops 1885325342 # Number of ops (including micro ops) simulated +host_inst_rate 98901 # Simulator instruction rate (inst/s) +host_op_rate 121761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45880544 # Simulator tick rate (ticks/s) +host_mem_usage 261988 # Number of bytes of host memory used +host_seconds 6477.65 # Real time elapsed on the host +sim_insts 640649298 # Number of instructions simulated +sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory -system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory +system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474992 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62035569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290424 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290424 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18565376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18587136 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29868 # Per bank write bursts -system.physmem.perBankRdBursts::1 29664 # Per bank write bursts -system.physmem.perBankRdBursts::2 29737 # Per bank write bursts -system.physmem.perBankRdBursts::3 29712 # Per bank write bursts -system.physmem.perBankRdBursts::4 29799 # Per bank write bursts -system.physmem.perBankRdBursts::5 29810 # Per bank write bursts -system.physmem.perBankRdBursts::6 29625 # Per bank write bursts -system.physmem.perBankRdBursts::7 29426 # Per bank write bursts -system.physmem.perBankRdBursts::8 29475 # Per bank write bursts -system.physmem.perBankRdBursts::9 29463 # Per bank write bursts -system.physmem.perBankRdBursts::10 29528 # Per bank write bursts -system.physmem.perBankRdBursts::11 29636 # Per bank write bursts -system.physmem.perBankRdBursts::12 29682 # Per bank write bursts -system.physmem.perBankRdBursts::13 29788 # Per bank write bursts -system.physmem.perBankRdBursts::14 29619 # Per bank write bursts -system.physmem.perBankRdBursts::15 29790 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18318 # Per bank write bursts +system.physmem.perBankRdBursts::1 18131 # Per bank write bursts +system.physmem.perBankRdBursts::2 18196 # Per bank write bursts +system.physmem.perBankRdBursts::3 18163 # Per bank write bursts +system.physmem.perBankRdBursts::4 18256 # Per bank write bursts +system.physmem.perBankRdBursts::5 18279 # Per bank write bursts +system.physmem.perBankRdBursts::6 18091 # Per bank write bursts +system.physmem.perBankRdBursts::7 17906 # Per bank write bursts +system.physmem.perBankRdBursts::8 17946 # Per bank write bursts +system.physmem.perBankRdBursts::9 17953 # Per bank write bursts +system.physmem.perBankRdBursts::10 18007 # Per bank write bursts +system.physmem.perBankRdBursts::11 18104 # Per bank write bursts +system.physmem.perBankRdBursts::12 18147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18252 # Per bank write bursts +system.physmem.perBankRdBursts::14 18085 # Per bank write bursts +system.physmem.perBankRdBursts::15 18250 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4171 # Per bank write bursts +system.physmem.perBankWrBursts::6 4170 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4090 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4091 # Per bank write bursts system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::15 4139 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 634728009000 # Total gap between requests +system.physmem.totGap 297198223500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474992 # Read request sizes (log2) +system.physmem.readPktSize::6 290424 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 235690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49717 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 106390 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 4985394000 # Total ticks spent queuing -system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads +system.physmem.totQLat 3531270750 # Total ticks spent queuing +system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.60 # Data bus utilization in percentage +system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing -system.physmem.readRowHits 298015 # Number of row buffer hits during reads -system.physmem.writeRowHits 49917 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes -system.physmem.avgGap 1173054.41 # Average gap between requests -system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states -system.physmem.memoryStateTime::REF 21194940000 # Time in different power states +system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing +system.physmem.readRowHits 199840 # Number of row buffer hits during reads +system.physmem.writeRowHits 49907 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes +system.physmem.avgGap 833604.16 # Average gap between requests +system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states +system.physmem.memoryStateTime::REF 9923940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states +system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54558418 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408916 # Transaction distribution -system.membus.trans_dist::ReadResp 408916 # Transaction distribution +system.membus.throughput 76774820 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224345 # Transaction distribution +system.membus.trans_dist::ReadResp 224344 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution -system.membus.trans_dist::ReadExReq 66076 # Transaction distribution -system.membus.trans_dist::ReadExResp 66076 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34629760 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution +system.membus.trans_dist::ReadExReq 66079 # Transaction distribution +system.membus.trans_dist::ReadExResp 66079 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22817344 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 478607550 # Number of BP lookups -system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups -system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits +system.cpu.branchPred.lookups 271863224 # Number of BP lookups +system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups +system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -364,519 +364,518 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1269456157 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 594396552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed -system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed +system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued -system.cpu.iq.rate 1.964874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued +system.cpu.iq.rate 1.934083 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12697 # number of nop insts executed -system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed -system.cpu.iew.exec_branches 329019811 # Number of branches executed -system.cpu.iew.exec_stores 429891953 # Number of stores executed -system.cpu.iew.exec_rate 1.909637 # Inst execution rate -system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1389701712 # num instructions producing a value -system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value +system.cpu.iew.exec_nop 633128 # number of nop insts executed +system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed +system.cpu.iew.exec_branches 162537737 # Number of branches executed +system.cpu.iew.exec_stores 207479483 # Number of stores executed +system.cpu.iew.exec_rate 1.878131 # Inst execution rate +system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back +system.cpu.iew.wb_producers 606518919 # num instructions producing a value +system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back +system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384381606 # Number of instructions committed -system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle +system.cpu.commit.committedInsts 640654410 # Number of instructions committed +system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908382478 # Number of memory references committed -system.cpu.commit.loads 631387181 # Number of loads committed -system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 298259106 # Number of branches committed -system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. -system.cpu.commit.function_calls 41577833 # Number of function calls committed. +system.cpu.commit.refs 381221434 # Number of memory references committed +system.cpu.commit.loads 252240938 # Number of loads committed +system.cpu.commit.membars 5740 # Number of memory barriers committed +system.cpu.commit.branches 137364859 # Number of branches committed +system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. +system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. +system.cpu.commit.function_calls 19275340 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 930022484 49.33% 49.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 11168279 0.59% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 1375288 0.07% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 6876469 0.36% 50.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 5501172 0.29% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 22010188 1.17% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 631387181 33.49% 85.31% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction -system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction +system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3962036316 # The number of ROB reads -system.cpu.rob.rob_writes 6083536675 # The number of ROB writes -system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384370590 # Number of Instructions Simulated -system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads -system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads -system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads -system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes -system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads -system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1926179188 # The number of ROB reads +system.cpu.rob.rob_writes 3042778169 # The number of ROB writes +system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 640649298 # Number of Instructions Simulated +system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads +system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads +system.cpu.int_regfile_writes 646986163 # number of integer regfile writes +system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads +system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes +system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads +system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes +system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads +system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 24993 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10545 # number of replacements +system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.825684 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 716098748 # Number of tag accesses -system.cpu.icache.tags.data_accesses 716098748 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 357999320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 357999320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 357999320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 357999320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 357999320 # number of overall hits -system.cpu.icache.overall_hits::total 357999320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34446 # number of overall misses -system.cpu.icache.overall_misses::total 34446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 570147243 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 570147243 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 570147243 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 570147243 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 358033766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 358033766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 358033766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 358033766 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16551.914388 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16551.914388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16551.914388 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1683 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1626.781544 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.794327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.794327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1664 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1549 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 415715422 # Number of tag accesses +system.cpu.icache.tags.data_accesses 415715422 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 207833630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 207833630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 207833630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 207833630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 207833630 # number of overall hits +system.cpu.icache.overall_hits::total 207833630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16808 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16808 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16808 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16808 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16808 # number of overall misses +system.cpu.icache.overall_misses::total 16808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373718245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373718245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373718245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373718245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373718245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373718245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 207850438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 207850438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 207850438 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 207850438 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 207850438 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 207850438 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000081 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000081 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000081 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000081 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000081 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000081 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22234.545752 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22234.545752 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1690 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60.107143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3230 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3230 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3230 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3230 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3230 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3230 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31216 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31216 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31216 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31216 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31216 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31216 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 454582253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 454582253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 454582253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 454582253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 454582253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 454582253 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14562.476070 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14562.476070 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14562.476070 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14562.476070 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14562.476070 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14562.476070 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2261 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2261 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2261 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2261 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2261 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2261 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14547 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 14547 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 14547 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 14547 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 14547 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 14547 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 287782750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 287782750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 287782750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 287782750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 287782750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 287782750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19782.962123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19782.962123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19782.962123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19782.962123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19782.962123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19782.962123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442210 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32678.682015 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1111317 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474958 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.339822 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257640 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32630.586328 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 527670 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290385 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.817139 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1315.086004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.777344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31312.818667 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040133 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001550 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.955591 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32748 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4974 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27020 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999390 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13864217 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13864217 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 24244 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1058074 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1082318 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96290 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96290 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 2747.858581 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.601052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29814.126695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.083858 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002094 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.909855 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995806 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32745 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4949 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27060 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999298 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7480211 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7480211 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 9862 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 492819 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 502681 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91367 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91367 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6436 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6436 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 24244 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1064510 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1088754 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 24244 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1064510 # number of overall hits -system.cpu.l2cache.overall_hits::total 1088754 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2440 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406500 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408940 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4530 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4530 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66076 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66076 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2440 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472576 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475016 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2440 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472576 # number of overall misses -system.cpu.l2cache.overall_misses::total 475016 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176349750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29369544500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29545894250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756102500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4756102500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 176349750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 34125647000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34301996750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 176349750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 34125647000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34301996750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 26684 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1464574 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1491258 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96290 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96290 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4533 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4533 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72512 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72512 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 26684 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1537086 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1563770 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 26684 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1537086 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1563770 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.091441 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277555 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.274225 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999338 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999338 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911242 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911242 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.091441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307449 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.303763 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.091441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307449 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.303763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72274.487705 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72249.801968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72249.949259 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71979.273866 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71979.273866 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72274.487705 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.976486 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72212.297586 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72274.487705 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.976486 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72212.297586 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 3232 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3232 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9862 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 496051 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 505913 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9862 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 496051 # number of overall hits +system.cpu.l2cache.overall_hits::total 505913 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2349 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 222019 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224368 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2334 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2334 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66079 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66079 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2349 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288098 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290447 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2349 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288098 # number of overall misses +system.cpu.l2cache.overall_misses::total 290447 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 172220250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16196026750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16368247000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5137976250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5137976250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 172220250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 21334003000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21506223250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 172220250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 21334003000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21506223250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12211 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 714838 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 727049 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91367 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91367 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2337 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2337 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12211 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 784149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 796360 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12211 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 784149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 796360 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192368 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.310586 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.308601 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998716 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.998716 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953370 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953370 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192368 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.367402 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.364718 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192368 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.367402 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.364718 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73316.411239 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72948.832082 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72952.680418 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77755.054556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77755.054556 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73316.411239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74051.201327 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74045.258687 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73316.411239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74051.201327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74045.258687 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,201 +887,217 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2438 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406478 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408916 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4530 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4530 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66076 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66076 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 472554 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 472554 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145569750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24308392500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24453962250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45304530 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45304530 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3923643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3923643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145569750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28232036000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28377605750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145569750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28232036000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28377605750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277540 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274209 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999338 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999338 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.303748 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.303748 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59708.675144 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59802.480085 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59801.920810 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2347 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221998 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224345 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2334 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2334 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66079 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66079 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2347 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288077 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2347 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288077 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290424 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 142668750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13415878250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13558547000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 23342334 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 23342334 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4297620250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4297620250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142668750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17713498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17856167250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142668750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17713498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17856167250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.310557 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308569 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998716 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998716 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953370 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953370 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.364689 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.364689 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60787.707712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.428445 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60436.145223 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59380.766088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59380.766088 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65037.610285 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65037.610285 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532989 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.399228 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 981387634 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1537085 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 638.473236 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 399634250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.399228 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999609 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 780052 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.850454 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 456274938 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 784148 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 581.873496 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 340792000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.850454 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999231 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999231 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2364 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 451 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1969885597 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1969885597 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 705264252 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 705264252 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276089331 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276089331 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 981353583 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 981353583 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 981353583 # number of overall hits -system.cpu.dcache.overall_hits::total 981353583 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1954339 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1954339 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 846347 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 846347 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 918547346 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 918547346 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 328318489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 328318489 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127934774 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127934774 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3905 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3905 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5745 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5745 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 456253263 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 456253263 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 456257168 # number of overall hits +system.cpu.dcache.overall_hits::total 456257168 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1596085 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1596085 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1016703 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1016703 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 156 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 156 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses -system.cpu.dcache.overall_misses::total 2800686 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked +system.cpu.dcache.demand_misses::cpu.data 2612788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2612788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2612944 # number of overall misses +system.cpu.dcache.overall_misses::total 2612944 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 134694562447 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 134694562447 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 458866051 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 458866051 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 458870112 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 458870112 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005694 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005694 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005694 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51552.044195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51548.966395 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3326 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.194444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96290 # number of writebacks -system.cpu.dcache.writebacks::total 96290 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489763 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489763 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769304 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769304 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 91367 # number of writebacks +system.cpu.dcache.writebacks::total 91367 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881385 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 881385 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 945064 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 945064 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1259067 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1259067 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1259067 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1259067 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464576 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464576 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77043 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77043 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541619 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541619 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41415183522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41415183522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4998292971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4998292971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46413476493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46413476493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46413476493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46413476493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002071 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002071 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001566 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001566 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1826449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1826449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1826449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1826449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 714700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 714700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71639 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71639 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 786486 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 786486 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 620dbb60e..a6a0dd3a8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.945613 # Number of seconds simulated -sim_ticks 945613126000 # Number of ticks simulated -final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.395727 # Number of seconds simulated +sim_ticks 395726778000 # Number of ticks simulated +final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1407956 # Simulator instruction rate (inst/s) -host_op_rate 1917442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 961716087 # Simulator tick rate (ticks/s) -host_mem_usage 309672 # Number of bytes of host memory used -host_seconds 983.26 # Real time elapsed on the host -sim_insts 1384381606 # Number of instructions simulated -sim_ops 1885336358 # Number of ops (including micro ops) simulated +host_inst_rate 935276 # Simulator instruction rate (inst/s) +host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 577711928 # Simulator tick rate (ticks/s) +host_mem_usage 250216 # Number of bytes of host memory used +host_seconds 684.99 # Real time elapsed on the host +sim_insts 640654410 # Number of instructions simulated +sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory -system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory -system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9675679644 # Throughput (bytes/s) -system.membus.data_through_bus 9149449674 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 2573511592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory +system.physmem.bytes_read::total 3718230108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2573511592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2573511592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory +system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 643377898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory +system.physmem.num_reads::total 893713136 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory +system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6503253596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2892699154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9395952750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6503253596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6503253596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1322421029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1322421029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10718373779 # Throughput (bytes/s) +system.membus.data_through_bus 4241547521 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -123,64 +123,66 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1891226253 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 791453557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1384381606 # Number of instructions committed -system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698868 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382479 # number of memory refs -system.cpu.num_load_insts 631387181 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.committedInsts 640654410 # Number of instructions committed +system.cpu.committedOps 788730069 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 2369173291 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1891226253 # Number of busy cycles +system.cpu.num_busy_cycles 791453557 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 298259106 # Number of branches fetched +system.cpu.Branches 137364859 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction -system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction -system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1885337770 # Class of executed instruction +system.cpu.op_class::total 788730743 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index baba5d53b..d4c7242b6 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.326119 # Number of seconds simulated -sim_ticks 2326118592000 # Number of ticks simulated -final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043695 # Number of seconds simulated +sim_ticks 1043695084000 # Number of ticks simulated +final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 706219 # Simulator instruction rate (inst/s) -host_op_rate 958037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1189016431 # Simulator tick rate (ticks/s) -host_mem_usage 318376 # Number of bytes of host memory used -host_seconds 1956.34 # Real time elapsed on the host -sim_insts 1381604339 # Number of instructions simulated -sim_ops 1874244941 # Number of ops (including micro ops) simulated +host_inst_rate 520727 # Simulator instruction rate (inst/s) +host_op_rate 639745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850028397 # Simulator tick rate (ticks/s) +host_mem_usage 259968 # Number of bytes of host memory used +host_seconds 1227.84 # Real time elapsed on the host +sim_insts 639366786 # Number of instructions simulated +sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory -system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 14864384 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408063 # Transaction distribution -system.membus.trans_dist::ReadResp 408063 # Transaction distribution -system.membus.trans_dist::Writeback 66099 # Transaction distribution +system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory +system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21818480 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34576320 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22771840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -137,117 +137,119 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4652237184 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 2087390168 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1381604339 # Number of instructions committed -system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698868 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382479 # number of memory refs -system.cpu.num_load_insts 631387181 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.committedInsts 639366786 # Number of instructions committed +system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4652237184 # Number of busy cycles +system.cpu.num_busy_cycles 2087390168 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 298259106 # Number of branches fetched +system.cpu.Branches 137364859 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction -system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction -system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1885337770 # Class of executed instruction -system.cpu.icache.tags.replacements 18364 # number of replacements -system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. +system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.icache.tags.replacements 8769 # number of replacements +system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits -system.cpu.icache.overall_hits::total 1390251699 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses -system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits +system.cpu.icache.overall_hits::total 643367691 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses +system.cpu.icache.overall_misses::total 10208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,123 +258,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 441378 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 256932 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1387 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31024 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13744605 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13744605 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96257 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96257 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18030 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1061270 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1079300 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18030 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1061270 # number of overall hits -system.cpu.l2cache.overall_hits::total 1079300 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1773 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408063 # number of ReadReq misses +system.cpu.l2cache.tags.tag_accesses 7430286 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8438 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 490970 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 499408 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91561 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8438 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 494200 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 502638 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8438 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 494200 # number of overall hits +system.cpu.l2cache.overall_hits::total 502638 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1770 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 221849 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 223619 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1773 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472383 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 474156 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1773 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472383 # number of overall misses -system.cpu.l2cache.overall_misses::total 474156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92202000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21127080000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21219282000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92202000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24563916000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24656118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92202000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24563916000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24656118000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96257 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96257 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1533653 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1553456 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 19803 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.089532 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278115 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.275592 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.089532 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.308012 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.305227 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.089532 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.308012 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.305227 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.384095 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.014704 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.012654 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.012654 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 1770 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 287942 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 289712 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses +system.cpu.l2cache.overall_misses::total 289712 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92118500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11536392000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11628510500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436883000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3436883000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 92118500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14973275000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15065393500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 92118500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14973275000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15065393500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91561 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.173393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311228 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.309282 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173393 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368145 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.365636 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,127 +383,135 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks -system.cpu.l2cache.writebacks::total 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1773 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408063 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks +system.cpu.l2cache.writebacks::total 66098 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1770 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221849 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 223619 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1773 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 472383 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1773 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 472383 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474156 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70926000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16251600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16322526000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1770 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287942 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70811000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8873960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8944771000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70926000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18895320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18966246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70926000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18895320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18966246000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278115 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.275592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.305227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70811000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11517680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11588491000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70811000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11517680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1529557 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 778046 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 568 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1040 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1796115775 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1796115775 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits -system.cpu.dcache.overall_hits::total 895737438 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses -system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits +system.cpu.dcache.overall_hits::total 378498833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses +system.cpu.dcache.overall_misses::total 782143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,60 +520,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks -system.cpu.dcache.writebacks::total 96257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks +system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) +system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |