diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing')
3 files changed, 275 insertions, 186 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 1b963b10c..90c413b65 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -202,7 +194,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 0aab67a06..8786d03ec 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:28:56 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:15:15 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 32a07ce20..22fcb32bd 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.046914 # Nu sim_ticks 46914279500 # Number of ticks simulated final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107347 # Simulator instruction rate (inst/s) -host_tick_rate 57007816 # Simulator tick rate (ticks/s) -host_mem_usage 216192 # Number of bytes of host memory used -host_seconds 822.94 # Real time elapsed on the host +host_inst_rate 145791 # Simulator instruction rate (inst/s) +host_op_rate 145791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77424105 # Simulator tick rate (ticks/s) +host_mem_usage 218104 # Number of bytes of host memory used +host_seconds 605.94 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11164096 # Number of bytes read from this memory system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory system.physmem.bytes_written 7712960 # Number of bytes written to this memory @@ -69,9 +71,10 @@ system.cpu.comNops 8748916 # Nu system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed system.cpu.comInts 30791227 # Number of Integer instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed -system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads @@ -125,26 +128,39 @@ system.cpu.icache.total_refs 12263478 # To system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1886.858130 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.921317 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12263478 # number of ReadReq hits -system.cpu.icache.demand_hits 12263478 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12263478 # number of overall hits -system.cpu.icache.ReadReq_misses 116984 # number of ReadReq misses -system.cpu.icache.demand_misses 116984 # number of demand (read+write) misses -system.cpu.icache.overall_misses 116984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 2068004000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 2068004000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12380462 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12380462 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.009449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.009449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.009449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 17677.665322 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 17677.665322 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 17677.665322 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1886.858130 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921317 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921317 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12263478 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12263478 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12263478 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12263478 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12263478 # number of overall hits +system.cpu.icache.overall_hits::total 12263478 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 116984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 116984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 116984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 116984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 116984 # number of overall misses +system.cpu.icache.overall_misses::total 116984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2068004000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2068004000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2068004000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2068004000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2068004000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2068004000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12380462 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12380462 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12380462 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12380462 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12380462 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12380462 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009449 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009449 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009449 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.665322 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 31328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 31328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 85656 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 85656 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31328 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 31328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 31328 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 31328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 31328 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 31328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 85656 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 85656 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 85656 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 85656 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 85656 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 85656 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1345401500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1345401500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1345401500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1345401500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1345401500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1345401500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use @@ -181,32 +200,49 @@ system.cpu.dcache.total_refs 34126014 # To system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4073.105766 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20180445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13945569 # number of WriteReq hits -system.cpu.dcache.demand_hits 34126014 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34126014 # number of overall hits -system.cpu.dcache.ReadReq_misses 96193 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 667808 # number of WriteReq misses -system.cpu.dcache.demand_misses 764001 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 764001 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39490722000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.045698 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 51689.359045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 51689.359045 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4073.105766 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994411 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994411 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180445 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945569 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126014 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126014 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126014 # number of overall hits +system.cpu.dcache.overall_hits::total 34126014 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667808 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667808 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764001 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764001 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764001 # number of overall misses +system.cpu.dcache.overall_misses::total 764001 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158649000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4158649000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35332073000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35332073000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39490722000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39490722000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39490722000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39490722000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43232.345389 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52907.531806 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161216 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 35426 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 524228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 559654 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 60767 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 204347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2088724500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 7254420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9343144500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9343144500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 161216 # number of writebacks +system.cpu.dcache.writebacks::total 161216 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35426 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35426 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524228 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524228 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559654 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559654 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559654 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559654 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343144500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9343144500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343144500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9343144500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 148060 # number of replacements system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use @@ -248,36 +292,75 @@ system.cpu.l2cache.total_refs 131331 # To system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3005.792321 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15657.764606 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.091730 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.477837 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 103294 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 115564 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 115564 # number of overall hits -system.cpu.l2cache.ReadReq_misses 42939 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 174439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 174439 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 2242306500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9096691500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9096691500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 146233 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 290003 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 290003 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.293634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.601508 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.601508 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52148.266729 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52148.266729 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15657.764606 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1362.413436 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1643.378886 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.477837 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.041578 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.050152 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.569567 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 76292 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 27002 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 103294 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 161216 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 161216 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 76292 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39272 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 115564 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 76292 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39272 # number of overall hits +system.cpu.l2cache.overall_hits::total 115564 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 9364 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 33575 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 42939 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9364 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165075 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174439 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9364 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165075 # number of overall misses +system.cpu.l2cache.overall_misses::total 174439 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 489614500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752692000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2242306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854385000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6854385000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 489614500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8607077000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9096691500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 489614500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8607077000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9096691500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 85656 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146233 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161216 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161216 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 85656 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290003 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 85656 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290003 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.109321 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554253 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109321 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.807817 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109321 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.807817 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -286,30 +369,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120515 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 42939 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 174439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 174439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1718628500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262711000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 6981339500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 6981339500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.601508 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.601508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 120515 # number of writebacks +system.cpu.l2cache.writebacks::total 120515 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9364 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33575 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 42939 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165075 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9364 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165075 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174439 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 375279000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343349500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1718628500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262711000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262711000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 375279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6981339500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 375279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606060500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6981339500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554253 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |