regressions: update stats due to branch predictor changes

The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

3 files changed, 43 insertions, 49 deletions

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 00b189ec1..81c2390c7 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
 memories=system.physmem
 num_work_ids=16
 readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 activity=0
+branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
 clock=500
 cpu_id=0
-defer_registration=false
 div16Latency=1
 div16RepeatRate=1
 div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
 fetchBuffSize=4
 function_trace=false
 function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
 itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
 multLatency=1
 multRepeatRate=1
 numThreads=1
-predType=tournament
 profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
+switched_out=false
 system=system
 threadModel=SMT
 tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
 [system.cpu.dcache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=2
 is_top_level=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=2
 size=262144
-subblock_size=0
 system=system
 tgts_per_mshr=20
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=2
 is_top_level=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=2
 size=131072
-subblock_size=0
 system=system
 tgts_per_mshr=20
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
@@ -163,21 +159,16 @@ assoc=8
 block_size=64
 clock=500
 forward_snoops=true
-hash_delay=1
 hit_latency=20
 is_top_level=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
 response_latency=20
 size=2097152
-subblock_size=0
 system=system
 tgts_per_mshr=12
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
@@ -204,7 +195,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 2318eb90a..41b47fff5 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:19:26
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:34:49
+gem5 executing on ribera.cs.wisc.edu
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 130fea357..8052f41c2 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.043266                       # Nu
 sim_ticks                                 43266024500                       # Number of ticks simulated
 final_tick                                43266024500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 113775                       # Simulator instruction rate (inst/s)
-host_op_rate                                   113775                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55722813                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252752                       # Number of bytes of host memory used
-host_seconds                                   776.45                       # Real time elapsed on the host
+host_inst_rate                                  92573                       # Simulator instruction rate (inst/s)
+host_op_rate                                    92573                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45339086                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308556                       # Number of bytes of host memory used
+host_seconds                                   954.28                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            454720                       # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits                     41713                       # Nu
 system.physmem.readRowHitRate                   91.81                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  36.59                       # Row buffer hit rate for writes
 system.physmem.avgGap                       154790.12                       # Average gap between requests
+system.cpu.branchPred.lookups                18742312                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12317439                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           4774431                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             15498318                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 4661486                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             30.077367                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1660962                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1030                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls                 4583                       # Nu
 system.cpu.numCycles                         86532050                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups          18742312                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted     12317439                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect      4774431                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups       15498318                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits           4661486                       # Number of BTB hits
-system.cpu.branch_predictor.usedRAS           1660962                       # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect         1030                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       30.077367                       # BTB Hit Percentage
 system.cpu.branch_predictor.predictedTaken      8071751                       # Number of Branches Predicted As Taken (True).
 system.cpu.branch_predictor.predictedNotTaken     10670561                       # Number of Branches Predicted As Not Taken (False).
 system.cpu.regfile_manager.intRegFileReads     74169472                       # Number of Reads from Int. Register File