diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-11-17 04:54:14 -0500 |
| commit | 6ed567d6002df081dd6cf2db6685d3e66c11272b (patch) | |
| tree | d6df4c0abaf10391c9ca9fb9dfc833737c979e37 /tests/long/se/50.vortex/ref/alpha/tru64/minor-timing | |
| parent | 74249f80df4e6128da38dfb5dbf5f61285c673a2 (diff) | |
| download | gem5-6ed567d6002df081dd6cf2db6685d3e66c11272b.tar.xz | |
alpha: Remove ALPHA tru64 support and associated tests
No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/minor-timing')
4 files changed, 0 insertions, 1727 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 46094eb94..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index a86af0918..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28063 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 61709224000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 0d9a67eb8..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.061709 # Number of seconds simulated -sim_ticks 61709224000 # Number of ticks simulated -final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 484192 # Simulator instruction rate (inst/s) -host_op_rate 484192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337853764 # Simulator tick rate (ticks/s) -host_mem_usage 263376 # Number of bytes of host memory used -host_seconds 182.65 # Real time elapsed on the host -sim_insts 88438073 # Number of instructions simulated -sim_ops 88438073 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165740 # Number of read requests accepted -system.physmem.writeReqs 115251 # Number of write requests accepted -system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10387 # Per bank write bursts -system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10068 # Per bank write bursts -system.physmem.perBankRdBursts::4 10353 # Per bank write bursts -system.physmem.perBankRdBursts::5 10360 # Per bank write bursts -system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10230 # Per bank write bursts -system.physmem.perBankRdBursts::8 10568 # Per bank write bursts -system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10568 # Per bank write bursts -system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10306 # Per bank write bursts -system.physmem.perBankRdBursts::13 10592 # Per bank write bursts -system.physmem.perBankRdBursts::14 10494 # Per bank write bursts -system.physmem.perBankRdBursts::15 10573 # Per bank write bursts -system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7281 # Per bank write bursts -system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7012 # Per bank write bursts -system.physmem.perBankWrBursts::4 7145 # Per bank write bursts -system.physmem.perBankWrBursts::5 7305 # Per bank write bursts -system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7164 # Per bank write bursts -system.physmem.perBankWrBursts::8 7246 # Per bank write bursts -system.physmem.perBankWrBursts::9 7071 # Per bank write bursts -system.physmem.perBankWrBursts::10 7213 # Per bank write bursts -system.physmem.perBankWrBursts::11 7126 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7351 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61709200500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165740 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115251 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # 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What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads -system.physmem.totQLat 3617300750 # Total ticks spent queuing -system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.28 # Data bus utilization in percentage -system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing -system.physmem.readRowHits 144262 # Number of row buffer hits during reads -system.physmem.writeRowHits 89468 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes -system.physmem.avgGap 219612.73 # Average gap between requests -system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) -system.physmem_0.averagePower 393.299410 # Core power per rank (mW) -system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states -system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) -system.physmem_1.averagePower 400.858918 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696527 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579387 # DTB read hits -system.cpu.dtb.read_misses 95377 # DTB read misses -system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674764 # DTB read accesses -system.cpu.dtb.write_hits 14666029 # DTB write hits -system.cpu.dtb.write_misses 8840 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674869 # DTB write accesses -system.cpu.dtb.data_hits 35245416 # DTB hits -system.cpu.dtb.data_misses 104217 # DTB misses -system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349633 # DTB accesses -system.cpu.itb.fetch_hits 25650137 # ITB hits -system.cpu.itb.fetch_misses 5179 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25655316 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 123418448 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88438073 # Number of instructions committed -system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.395535 # CPI: cycles per instruction -system.cpu.ipc 0.716571 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction -system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction -system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::MemRead 20366476 23.03% 83.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 14619024 16.53% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 310 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked -system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200809 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits -system.cpu.dcache.overall_hits::total 34647996 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses -system.cpu.dcache.overall_misses::total 341611 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168117 # number of writebacks -system.cpu.dcache.writebacks::total 168117 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136509 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136706 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136706 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61338 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61338 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153962 # number of replacements -system.cpu.icache.tags.tagsinuse 1929.475732 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25494126 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 156010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.413409 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 43906590500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1929.475732 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51456284 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51456284 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25494126 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25494126 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25494126 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25494126 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25494126 # number of overall hits -system.cpu.icache.overall_hits::total 25494126 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 156011 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 156011 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 156011 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 156011 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 156011 # number of overall misses -system.cpu.icache.overall_misses::total 156011 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2690499000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2690499000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2690499000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2690499000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25650137 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153962 # number of writebacks -system.cpu.icache.writebacks::total 153962 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 156011 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 156011 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 156011 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 156011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 135280 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31691.220276 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 547521 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168048 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.258123 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 14447297000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 710.430921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1986.776331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28994.013023 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060632 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.884827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.967139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 8856 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22759 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5893544 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5893544 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153962 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153962 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195175 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149161 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits -system.cpu.l2cache.overall_hits::total 195175 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27983 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27983 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6850 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158891 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165741 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6850 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158891 # number of overall misses -system.cpu.l2cache.overall_misses::total 165741 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 734127500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14480055000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15214182500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 734127500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14480055000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15214182500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 156011 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360916 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 156011 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360916 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043907 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775437 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.459223 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043907 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775437 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.459223 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115252 # number of writebacks -system.cpu.l2cache.writebacks::total 115252 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135280 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34832 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution -system.membus.trans_dist::CleanEvict 15886 # Transaction distribution -system.membus.trans_dist::ReadExReq 130908 # Transaction distribution -system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165740 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165740 # Request fanout histogram -system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |