diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/se/50.vortex/ref/alpha/tru64/minor-timing | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/minor-timing')
4 files changed, 662 insertions, 580 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini index a6321b5a0..4117f093b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,9 +26,16 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -55,6 +64,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -97,12 +107,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -118,11 +133,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -130,13 +152,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -146,6 +173,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -154,8 +182,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -553,13 +586,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -569,6 +607,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -577,8 +616,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -602,13 +646,18 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -618,6 +667,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -626,19 +676,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -646,6 +708,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -660,7 +729,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin kvmInSE=false @@ -692,9 +761,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -738,6 +813,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -749,7 +825,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr index f0a9a7c93..e0bca4e4e 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr @@ -1,5 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout index 9dd4d1ffb..dcc24233a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 20:54:01 -gem5 started Sep 14 2015 21:22:43 -gem5 executing on ribera.cs.wisc.edu -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing +gem5 compiled Jul 19 2016 12:23:51 +gem5 started Jul 21 2016 14:09:29 +gem5 executing on e108600-lin, pid 4306 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 59549031000 because target called exit() +Exiting @ tick 60000593000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 7d04a6897..6234d30e2 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059447 # Number of seconds simulated -sim_ticks 59447065000 # Number of ticks simulated -final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060001 # Number of seconds simulated +sim_ticks 60000593000 # Number of ticks simulated +final_tick 60000593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 518825 # Simulator instruction rate (inst/s) -host_op_rate 518825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 348748418 # Simulator tick rate (ticks/s) -host_mem_usage 305412 # Number of bytes of host memory used -host_seconds 170.46 # Real time elapsed on the host +host_inst_rate 262235 # Simulator instruction rate (inst/s) +host_op_rate 262235 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177912819 # Simulator tick rate (ticks/s) +host_mem_usage 257844 # Number of bytes of host memory used +host_seconds 337.25 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory -system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 432832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 432832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7326016 # Number of bytes written to this memory -system.physmem.bytes_written::total 7326016 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6763 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158587 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165350 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114469 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114469 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7280965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170732870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178013835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7280965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7280965 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 123235958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 123235958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 123235958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7280965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170732870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301249793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165350 # Number of read requests accepted -system.physmem.writeReqs 114469 # Number of write requests accepted -system.physmem.readBursts 165350 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114469 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10581952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7323968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10582400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7326016 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 433344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10150272 # Number of bytes read from this memory +system.physmem.bytes_read::total 10583616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 433344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 433344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7325952 # Number of bytes written to this memory +system.physmem.bytes_written::total 7325952 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158598 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165369 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114468 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114468 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7222329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169169528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 176391857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7222329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7222329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122097993 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122097993 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122097993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7222329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169169528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 298489850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165369 # Number of read requests accepted +system.physmem.writeReqs 114468 # Number of write requests accepted +system.physmem.readBursts 165369 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114468 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10583232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7324288 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10583616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7325952 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10315 # Per bank write bursts -system.physmem.perBankRdBursts::1 10360 # Per bank write bursts +system.physmem.perBankRdBursts::0 10322 # Per bank write bursts +system.physmem.perBankRdBursts::1 10363 # Per bank write bursts system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10057 # Per bank write bursts -system.physmem.perBankRdBursts::4 10348 # Per bank write bursts +system.physmem.perBankRdBursts::3 10055 # Per bank write bursts +system.physmem.perBankRdBursts::4 10347 # Per bank write bursts system.physmem.perBankRdBursts::5 10343 # Per bank write bursts -system.physmem.perBankRdBursts::6 9775 # Per bank write bursts -system.physmem.perBankRdBursts::7 10207 # Per bank write bursts -system.physmem.perBankRdBursts::8 10536 # Per bank write bursts -system.physmem.perBankRdBursts::9 10606 # Per bank write bursts -system.physmem.perBankRdBursts::10 10500 # Per bank write bursts -system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10273 # Per bank write bursts -system.physmem.perBankRdBursts::13 10559 # Per bank write bursts -system.physmem.perBankRdBursts::14 10465 # Per bank write bursts -system.physmem.perBankRdBursts::15 10565 # Per bank write bursts +system.physmem.perBankRdBursts::6 9774 # Per bank write bursts +system.physmem.perBankRdBursts::7 10209 # Per bank write bursts +system.physmem.perBankRdBursts::8 10543 # Per bank write bursts +system.physmem.perBankRdBursts::9 10609 # Per bank write bursts +system.physmem.perBankRdBursts::10 10499 # Per bank write bursts +system.physmem.perBankRdBursts::11 10227 # Per bank write bursts +system.physmem.perBankRdBursts::12 10274 # Per bank write bursts +system.physmem.perBankRdBursts::13 10565 # Per bank write bursts +system.physmem.perBankRdBursts::14 10463 # Per bank write bursts +system.physmem.perBankRdBursts::15 10564 # Per bank write bursts system.physmem.perBankWrBursts::0 7163 # Per bank write bursts system.physmem.perBankWrBursts::1 7274 # Per bank write bursts system.physmem.perBankWrBursts::2 7296 # Per bank write bursts -system.physmem.perBankWrBursts::3 7002 # Per bank write bursts +system.physmem.perBankWrBursts::3 7001 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7186 # Per bank write bursts +system.physmem.perBankWrBursts::5 7187 # Per bank write bursts system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7099 # Per bank write bursts -system.physmem.perBankWrBursts::8 7226 # Per bank write bursts -system.physmem.perBankWrBursts::9 6999 # Per bank write bursts +system.physmem.perBankWrBursts::7 7100 # Per bank write bursts +system.physmem.perBankWrBursts::8 7227 # Per bank write bursts +system.physmem.perBankWrBursts::9 7003 # Per bank write bursts system.physmem.perBankWrBursts::10 7117 # Per bank write bursts -system.physmem.perBankWrBursts::11 7034 # Per bank write bursts +system.physmem.perBankWrBursts::11 7031 # Per bank write bursts system.physmem.perBankWrBursts::12 6992 # Per bank write bursts -system.physmem.perBankWrBursts::13 7299 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts +system.physmem.perBankWrBursts::13 7301 # Per bank write bursts +system.physmem.perBankWrBursts::14 7308 # Per bank write bursts +system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59447041000 # Total gap between requests +system.physmem.totGap 60000569500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165350 # Read request sizes (log2) +system.physmem.readPktSize::6 165369 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114469 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114468 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,127 +194,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.365172 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.328231 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.549756 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19615 35.86% 35.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11787 21.55% 57.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5586 10.21% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3666 6.70% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2860 5.23% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2087 3.82% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1603 2.93% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1458 2.67% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6030 11.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54692 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.476853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.379045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7039 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.137094 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.166991 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.705237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19617 35.84% 35.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11794 21.55% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5683 10.38% 67.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3657 6.68% 74.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2805 5.12% 79.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2027 3.70% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1612 2.95% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1505 2.75% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6036 11.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54736 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7044 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.474162 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.252876 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7042 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.250639 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.234557 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.758479 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6275 89.11% 89.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.16% 89.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 574 8.15% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 150 2.13% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.26% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 9 0.13% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads -system.physmem.totQLat 1988923000 # Total ticks spent queuing -system.physmem.totMemAccLat 5089104250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12029.07 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7044 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.246735 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.230854 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.753728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6287 89.25% 89.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 12 0.17% 89.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 574 8.15% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 138 1.96% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 18 0.26% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 7 0.10% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7044 # Writes before turning the bus around for reads +system.physmem.totQLat 1985984500 # Total ticks spent queuing +system.physmem.totMemAccLat 5086540750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12009.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30779.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 123.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.01 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 123.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30759.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 176.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 176.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.35 # Data bus utilization in percentage -system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.33 # Data bus utilization in percentage +system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing -system.physmem.readRowHits 143858 # Number of row buffer hits during reads -system.physmem.writeRowHits 81218 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.95 # Row buffer hit rate for writes -system.physmem.avgGap 212448.19 # Average gap between requests -system.physmem.pageHitRate 80.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199274040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108730875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636347400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 369068400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12411408285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24777095250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42384271290 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.053838 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41070575000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1984840000 # Time in different power states +system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing +system.physmem.readRowHits 143816 # Number of row buffer hits during reads +system.physmem.writeRowHits 81240 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.97 # Row buffer hit rate for writes +system.physmem.avgGap 214412.57 # Average gap between requests +system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 198964080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108561750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636386400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369061920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12421358775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25100061000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42752848725 # Total energy per rank (pJ) +system.physmem_0.averagePower 712.626862 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41606215000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2003300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16385091250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16383815000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213940440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116733375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652860000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 372152880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13085746785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24185582250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42509362770 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.158080 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40083292000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1984840000 # Time in different power states +system.physmem_1.actEnergy 214545240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 117063375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652945800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 372211200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13100937570 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24503939250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42880097235 # Total energy per rank (pJ) +system.physmem_1.averagePower 714.747907 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40611255500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2003300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17379160000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14660042 # Number of BP lookups -system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9866507 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6346497 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14695118 # Number of BP lookups +system.cpu.branchPred.condPredicted 9500860 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 385258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10182600 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6367092 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.323646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708762 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84355 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37443 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31778 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5665 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7605 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.529138 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712185 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84621 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37568 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5776 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20565775 # DTB read hits -system.cpu.dtb.read_misses 97355 # DTB read misses -system.cpu.dtb.read_acv 8 # DTB read access violations -system.cpu.dtb.read_accesses 20663130 # DTB read accesses -system.cpu.dtb.write_hits 14665271 # DTB write hits -system.cpu.dtb.write_misses 9409 # DTB write misses +system.cpu.dtb.read_hits 20578668 # DTB read hits +system.cpu.dtb.read_misses 95435 # DTB read misses +system.cpu.dtb.read_acv 10 # DTB read access violations +system.cpu.dtb.read_accesses 20674103 # DTB read accesses +system.cpu.dtb.write_hits 14665915 # DTB write hits +system.cpu.dtb.write_misses 8842 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674680 # DTB write accesses -system.cpu.dtb.data_hits 35231046 # DTB hits -system.cpu.dtb.data_misses 106764 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 35337810 # DTB accesses -system.cpu.itb.fetch_hits 25585531 # ITB hits -system.cpu.itb.fetch_misses 5208 # ITB misses +system.cpu.dtb.write_accesses 14674757 # DTB write accesses +system.cpu.dtb.data_hits 35244583 # DTB hits +system.cpu.dtb.data_misses 104277 # DTB misses +system.cpu.dtb.data_acv 10 # DTB access violations +system.cpu.dtb.data_accesses 35348860 # DTB accesses +system.cpu.itb.fetch_hits 25646396 # ITB hits +system.cpu.itb.fetch_misses 5177 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25590739 # ITB accesses +system.cpu.itb.fetch_accesses 25651573 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,16 +327,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 59447065000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 118894130 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60000593000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120001186 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1097381 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1084586 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.344377 # CPI: cycles per instruction -system.cpu.ipc 0.743839 # IPC: instructions per cycle +system.cpu.cpi 1.356895 # CPI: cycles per instruction +system.cpu.ipc 0.736977 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -373,106 +372,106 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200766 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.952954 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 687650500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.673886 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993817 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993817 # Average percentage of cache occupancy +system.cpu.tickCycles 91986001 # Number of cycles that the object actually ticked +system.cpu.idleCycles 28015185 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200807 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.707874 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34647558 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204903 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.092488 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 690770500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.707874 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # 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Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333259 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34612040 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34612040 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34612040 # number of overall hits -system.cpu.dcache.overall_hits::total 34612040 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89411 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89411 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280118 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280118 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369529 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369529 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369529 # number of overall misses -system.cpu.dcache.overall_misses::total 369529 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4770299000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4770299000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21700228000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21700228000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26470527000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26470527000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26470527000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26470527000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20368192 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20368192 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70183301 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70183301 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314289 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314289 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333269 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333269 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34647558 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34647558 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34647558 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24448426000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24448426000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24448426000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24448426000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20375822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20375822 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34981569 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34981569 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34981569 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34981569 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010564 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010564 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010564 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010564 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53352.484594 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53352.484594 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77468.166987 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77468.166987 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71633.151931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71633.151931 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 34989199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44505.379227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44505.379227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77505.378283 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77505.378283 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71561.744638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71561.744638 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168424 # number of writebacks -system.cpu.dcache.writebacks::total 168424 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136555 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136555 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164667 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61299 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61299 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143563 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143563 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204862 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2681247500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2681247500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10975422500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10975422500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13656670000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13656670000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13656670000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13656670000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168446 # number of writebacks +system.cpu.dcache.writebacks::total 168446 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136541 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 136738 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 136738 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 136738 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 136738 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61336 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61336 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204903 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204903 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204903 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204903 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2673829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2673829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10980283500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10980283500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13654113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13654113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13654113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13654113000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -481,330 +480,332 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43740.477006 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43740.477006 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76450.216978 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76450.216978 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 152872 # number of replacements -system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 154920 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 164.153176 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42235793500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1932.382407 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943546 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943546 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43593.150841 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43593.150841 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76481.945712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76481.945712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 153927 # number of replacements +system.cpu.icache.tags.tagsinuse 1931.746995 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25490420 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155975 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.426318 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42594058500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1931.746995 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943236 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943236 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1039 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1033 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 801 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51325982 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51325982 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25430610 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25430610 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25430610 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25430610 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25430610 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 114469 # number of writebacks -system.cpu.l2cache.writebacks::total 114469 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 114468 # number of writebacks +system.cpu.l2cache.writebacks::total 114468 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 470607500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11274251000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11744858500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911670 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911670 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043661 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451956 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451956 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459585 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459585 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71193.722638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71193.722638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.531047 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.531047 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70713.452931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70713.452931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 713421 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 353638 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911651 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911651 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043417 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451855 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451855 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.458242 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774015 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.458242 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71230.473018 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71230.473018 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69493.133491 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69493.133491 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70409.272957 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70409.272957 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69493.133491 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71086.968310 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69493.133491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71086.968310 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715613 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354734 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4027 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51255 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143564 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143564 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 154921 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61298 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462713 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1073203 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19698688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43588992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133382 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 493165 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008186 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.090105 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153927 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51284 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 155976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61336 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19833728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23894336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43728064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133391 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7325952 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 494270 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008147 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.089894 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 489128 99.18% 99.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4037 0.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 490243 99.19% 99.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4027 0.81% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 493165 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 678006500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 494270 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 680179500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 232381497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 233962999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307359989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34467 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution -system.membus.trans_dist::CleanEvict 14990 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34486 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114468 # Transaction distribution +system.membus.trans_dist::CleanEvict 15010 # Transaction distribution system.membus.trans_dist::ReadExReq 130883 # Transaction distribution system.membus.trans_dist::ReadExResp 130883 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34467 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460159 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17908416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17908416 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 34486 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460216 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460216 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17909568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17909568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 294809 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 294847 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294809 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294847 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294809 # Request fanout histogram -system.membus.reqLayer0.occupancy 822950500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294847 # Request fanout histogram +system.membus.reqLayer0.occupancy 819183500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 872961750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 873079500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |