stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

1 files changed, 16 insertions, 5 deletions

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 48bad98ae..7d04a6897 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.059447                       # Nu
 sim_ticks                                 59447065000                       # Number of ticks simulated
 final_tick                                59447065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 249746                       # Simulator instruction rate (inst/s)
-host_op_rate                                   249746                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              167876675                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256840                       # Number of bytes of host memory used
-host_seconds                                   354.11                       # Real time elapsed on the host
+host_inst_rate                                 518825                       # Simulator instruction rate (inst/s)
+host_op_rate                                   518825                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              348748418                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305412                       # Number of bytes of host memory used
+host_seconds                                   170.46                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            432832                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10149568                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10582400                       # Number of bytes read from this memory
@@ -279,6 +280,7 @@ system.physmem_1.memoryStateTime::REF      1984840000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT     17372590500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups                14660042                       # Number of BP lookups
 system.cpu.branchPred.condPredicted           9484785                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            381684                       # Number of conditional branches incorrect
@@ -326,6 +328,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON     59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        118894130                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -372,6 +375,7 @@ system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Cl
 system.cpu.op_class_0::total                 88438073                       # Class of committed instruction
 system.cpu.tickCycles                        91425505                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                        27468625                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            200766                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          4070.673886                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            34612040                       # Total number of references to valid blocks.
@@ -388,6 +392,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2         3360
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          70168000                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         70168000                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     20278781                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20278781                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     14333259                       # number of WriteReq hits
@@ -484,6 +489,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements            152872                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1932.382407                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            25430610                       # Total number of references to valid blocks.
@@ -502,6 +508,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4          798
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses          51325982                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses         51325982                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     25430610                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        25430610                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      25430610                       # number of demand (read+write) hits
@@ -570,6 +577,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334
 system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           133382                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30429.048447                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             403995                       # Total number of references to valid blocks.
@@ -592,6 +600,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4          124
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979919                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          6016424                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         6016424                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       168424                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       168424                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks       152872                       # number of WritebackClean hits
@@ -738,6 +747,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0
 system.cpu.toL2Bus.snoop_filter.tot_snoops         4037                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4037                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        216218                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       282893                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean       152872                       # Transaction distribution
@@ -770,6 +780,7 @@ system.cpu.toL2Bus.respLayer0.occupancy     232381497                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     307297491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED  59447065000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              34467                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty       114469                       # Transaction distribution
 system.membus.trans_dist::CleanEvict            14990                       # Transaction distribution