stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

1 files changed, 5 insertions, 14 deletions

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 7a3a9c70d..c69a77e9f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.059447                       # Nu
 sim_ticks                                 59447065000                       # Number of ticks simulated
 final_tick                                59447065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 412945                       # Simulator instruction rate (inst/s)
-host_op_rate                                   412945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              277576735                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261724                       # Number of bytes of host memory used
-host_seconds                                   214.16                       # Real time elapsed on the host
+host_inst_rate                                 371878                       # Simulator instruction rate (inst/s)
+host_op_rate                                   371878                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              249972170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261720                       # Number of bytes of host memory used
+host_seconds                                   237.81                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -442,8 +442,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168424                       # number of writebacks
 system.cpu.dcache.writebacks::total            168424                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28112                       # number of ReadReq MSHR hits
@@ -486,7 +484,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            152872                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1932.382407                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            25430610                       # Total number of references to valid blocks.
@@ -547,8 +544,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks       152872                       # number of writebacks
 system.cpu.icache.writebacks::total            152872                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154921                       # number of ReadReq MSHR misses
@@ -575,7 +570,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334
 system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           133382                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30429.048447                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             403995                       # Total number of references to valid blocks.
@@ -684,8 +678,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114469                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114469                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          115                       # number of CleanEvict MSHR misses
@@ -740,7 +732,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       713421                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       353638                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.