stats: changes due to recent changesets.

1 files changed, 133 insertions, 97 deletions

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 1993a40dc..47efecce5 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,33 +4,37 @@ sim_seconds                                  0.058585                       # Nu
 sim_ticks                                 58584661500                       # Number of ticks simulated
 final_tick                                58584661500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 346754                       # Simulator instruction rate (inst/s)
-host_op_rate                                   346754                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              229702503                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303900                       # Number of bytes of host memory used
-host_seconds                                   255.05                       # Real time elapsed on the host
+host_inst_rate                                 201524                       # Simulator instruction rate (inst/s)
+host_op_rate                                   201524                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              133496887                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290684                       # Number of bytes of host memory used
+host_seconds                                   438.85                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst          10664384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            516608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10147776                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10664384                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       516608                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          516608                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      7299072                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           7299072                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             166631                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               8072                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158559                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                166631                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          114048                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               114048                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            182033722                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              8818144                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            173215578                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total               182033722                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst         8818144                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total            8818144                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks         124590154                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total              124590154                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks         124590154                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           182033722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8818144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           173215578                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              306623876                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        166631                       # Number of read requests accepted
 system.physmem.writeReqs                       114048                       # Number of write requests accepted
@@ -335,8 +339,8 @@ system.cpu.dcache.tags.total_refs            34616515                       # To
 system.cpu.dcache.tags.sampled_refs            204872                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            168.966550                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         644809250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.523211                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.994024                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4071.523211                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.994024                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.994024                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
@@ -345,53 +349,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2         3298
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          70176892                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         70176892                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     20283193                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     20283193                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20283193                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     14333322                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14333322                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       14333322                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst      34616515                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      34616515                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         34616515                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     34616515                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     34616515                       # number of overall hits
 system.cpu.dcache.overall_hits::total        34616515                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst        89440                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data        89440                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total         89440                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       280055                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       280055                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       280055                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       369495                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data       369495                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total         369495                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       369495                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data       369495                       # number of overall misses
 system.cpu.dcache.overall_misses::total        369495                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   4407640500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4407640500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total   4407640500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  19996177500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19996177500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total  19996177500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  24403818000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  24403818000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::total  24403818000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  24403818000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  24403818000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  24403818000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     20372633                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     20372633                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20372633                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     34986010                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     34986010                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     34986010                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     34986010                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34986010                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     34986010                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.004390                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004390                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.004390                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.019164                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019164                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.019164                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.010561                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010561                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.010561                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.010561                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010561                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.010561                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49280.417039                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49280.417039                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71400.894467                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71400.894467                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66046.409288                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66046.409288                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total 66046.409288                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66046.409288                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66046.409288                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 66046.409288                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -403,45 +407,45 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168546                       # number of writebacks
 system.cpu.dcache.writebacks::total            168546                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        28125                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28125                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total        28125                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       136498                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136498                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total       136498                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       164623                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       164623                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total       164623                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       164623                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       164623                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total       164623                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        61315                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61315                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        61315                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       143557                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143557                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       143557                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       204872                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       204872                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total       204872                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       204872                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       204872                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204872                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2422248250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2422248250                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total   2422248250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   9931035500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9931035500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total   9931035500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  12353283750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12353283750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::total  12353283750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  12353283750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12353283750                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total  12353283750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009824                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009824                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009824                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.005856                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.005856                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39504.986545                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39504.986545                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39504.986545                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69178.343794                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69178.343794                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69178.343794                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60297.569946                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60297.569946                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60297.569946                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60297.569946                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60297.569946                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 60297.569946                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            153786                       # number of replacements
@@ -537,9 +541,11 @@ system.cpu.l2cache.tags.sampled_refs           164780                       # Sa
 system.cpu.l2cache.tags.avg_refs             1.339076                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks 26240.320965                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4237.109970                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2376.783596                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1860.326375                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.800791                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.129306                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072534                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.056773                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.930097                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32076                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
@@ -550,57 +556,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4          113
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978882                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          4542362                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         4542362                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       181399                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       147762                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        33637                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         181399                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks       168546                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       168546                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst        12676                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12676                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        12676                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       194075                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       147762                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46313                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          194075                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       194075                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       147762                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46313                       # number of overall hits
 system.cpu.l2cache.overall_hits::total         194075                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        35750                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst         8073                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        27677                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        35750                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       130882                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130882                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       130882                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       166632                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         8073                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158559                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        166632                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       166632                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst         8073                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158559                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       166632                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2603729750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    579593000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2024136750                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total   2603729750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9660681500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9660681500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total   9660681500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  12264411250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    579593000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11684818250                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total  12264411250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  12264411250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    579593000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11684818250                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total  12264411250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       217149                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       155835                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        61314                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       217149                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks       168546                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       168546                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       143558                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143558                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       143558                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       360707                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       155835                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       204872                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       360707                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       360707                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       155835                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       204872                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       360707                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.164634                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.051805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.451398                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.164634                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.911701                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911701                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.911701                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461959                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.051805                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.773942                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.461959                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461959                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.051805                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.773942                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.461959                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72831.601399                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71794.004707                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73134.254074                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 72831.601399                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73812.147583                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73812.147583                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73812.147583                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73601.776670                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71794.004707                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73693.819020                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 73601.776670                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73601.776670                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71794.004707                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73693.819020                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 73601.776670                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -612,37 +636,49 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114048                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114048                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        35750                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         8073                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27677                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total        35750                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       130882                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130882                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       130882                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       166632                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8073                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158559                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       166632                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       166632                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8073                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158559                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       166632                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2149088750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    478164000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1670924750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2149088750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7975554000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7975554000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7975554000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10124642750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    478164000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9646478750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total  10124642750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10124642750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    478164000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9646478750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total  10124642750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.164634                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.051805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.451398                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.164634                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.911701                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911701                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911701                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461959                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.051805                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773942                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.461959                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461959                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.051805                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773942                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.461959                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60114.370629                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59230.026013                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60372.321783                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60114.370629                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60936.981403                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60936.981403                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60936.981403                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60760.494683                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59230.026013                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60838.418191                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60760.494683                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60760.494683                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59230.026013                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60838.418191                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         217149                       # Transaction distribution