diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/50.vortex/ref/alpha/tru64/o3-timing | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/o3-timing')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 1572 |
1 files changed, 789 insertions, 783 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index bea1e6fc8..b43434371 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022357 # Number of seconds simulated -sim_ticks 22356634500 # Number of ticks simulated -final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022297 # Number of seconds simulated +sim_ticks 22296591500 # Number of ticks simulated +final_tick 22296591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213363 # Simulator instruction rate (inst/s) -host_op_rate 213363 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59931818 # Simulator tick rate (ticks/s) -host_mem_usage 308400 # Number of bytes of host memory used -host_seconds 373.03 # Real time elapsed on the host +host_inst_rate 221726 # Simulator instruction rate (inst/s) +host_op_rate 221726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62113736 # Simulator tick rate (ticks/s) +host_mem_usage 308500 # Number of bytes of host memory used +host_seconds 358.96 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 471552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10150720 # Number of bytes read from this memory -system.physmem.bytes_read::total 10622272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 471552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 471552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7318272 # Number of bytes written to this memory -system.physmem.bytes_written::total 7318272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158605 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165973 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114348 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114348 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21092262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454036139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 475128401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21092262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21092262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327342293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327342293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327342293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21092262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454036139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802470694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165973 # Number of read requests accepted -system.physmem.writeReqs 114348 # Number of write requests accepted -system.physmem.readBursts 165973 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114348 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10621952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 7316672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10622272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7318272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory +system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7322432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7322432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114413 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114413 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18387743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455370768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 473758511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18387743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18387743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 328410376 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 328410376 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 328410376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18387743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455370768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 802168888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165050 # Number of read requests accepted +system.physmem.writeReqs 114413 # Number of write requests accepted +system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114413 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7320896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7322432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10420 # Per bank write bursts -system.physmem.perBankRdBursts::1 10451 # Per bank write bursts -system.physmem.perBankRdBursts::2 10285 # Per bank write bursts -system.physmem.perBankRdBursts::3 10056 # Per bank write bursts -system.physmem.perBankRdBursts::4 10402 # Per bank write bursts -system.physmem.perBankRdBursts::5 10375 # Per bank write bursts -system.physmem.perBankRdBursts::6 9822 # Per bank write bursts -system.physmem.perBankRdBursts::7 10280 # Per bank write bursts -system.physmem.perBankRdBursts::8 10559 # Per bank write bursts -system.physmem.perBankRdBursts::9 10640 # Per bank write bursts -system.physmem.perBankRdBursts::10 10517 # Per bank write bursts -system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10263 # Per bank write bursts -system.physmem.perBankRdBursts::13 10582 # Per bank write bursts -system.physmem.perBankRdBursts::14 10475 # Per bank write bursts -system.physmem.perBankRdBursts::15 10613 # Per bank write bursts -system.physmem.perBankWrBursts::0 7161 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 14730 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10292 # Per bank write bursts +system.physmem.perBankRdBursts::1 10329 # Per bank write bursts +system.physmem.perBankRdBursts::2 10209 # Per bank write bursts +system.physmem.perBankRdBursts::3 10020 # Per bank write bursts +system.physmem.perBankRdBursts::4 10344 # Per bank write bursts +system.physmem.perBankRdBursts::5 10314 # Per bank write bursts +system.physmem.perBankRdBursts::6 9779 # Per bank write bursts +system.physmem.perBankRdBursts::7 10195 # Per bank write bursts +system.physmem.perBankRdBursts::8 10531 # Per bank write bursts +system.physmem.perBankRdBursts::9 10599 # Per bank write bursts +system.physmem.perBankRdBursts::10 10453 # Per bank write bursts +system.physmem.perBankRdBursts::11 10204 # Per bank write bursts +system.physmem.perBankRdBursts::12 10247 # Per bank write bursts +system.physmem.perBankRdBursts::13 10532 # Per bank write bursts +system.physmem.perBankRdBursts::14 10447 # Per bank write bursts +system.physmem.perBankRdBursts::15 10549 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts system.physmem.perBankWrBursts::1 7267 # Per bank write bursts system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::3 7000 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6835 # Per bank write bursts -system.physmem.perBankWrBursts::7 7095 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6995 # Per bank write bursts -system.physmem.perBankWrBursts::10 7101 # Per bank write bursts -system.physmem.perBankWrBursts::11 6988 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7292 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::6 6836 # Per bank write bursts +system.physmem.perBankWrBursts::7 7102 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::9 7001 # Per bank write bursts +system.physmem.perBankWrBursts::10 7100 # Per bank write bursts +system.physmem.perBankWrBursts::11 7020 # Per bank write bursts +system.physmem.perBankWrBursts::12 6992 # Per bank write bursts +system.physmem.perBankWrBursts::13 7297 # Per bank write bursts system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22356603500 # Total gap between requests +system.physmem.totGap 22296560500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165973 # Read request sizes (log2) +system.physmem.readPktSize::6 165050 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114348 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 52267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32162 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114413 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,125 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.051408 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.164629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.365120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18284 34.97% 34.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10551 20.18% 55.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5984 11.44% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2964 5.67% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2982 5.70% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1592 3.04% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1956 3.74% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 963 1.84% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7012 13.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52288 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.745743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.273336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6986 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.858612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.924906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.625607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18434 35.24% 35.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10645 20.35% 55.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5863 11.21% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2906 5.56% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2975 5.69% 78.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1493 2.85% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2022 3.87% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 988 1.89% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6984 13.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52310 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.610300 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 338.218951 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6987 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6989 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.357562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.328073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.050353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6097 87.24% 87.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.43% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 474 6.78% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 201 2.88% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 97 1.39% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.70% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 24 0.34% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 8 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6989 # Writes before turning the bus around for reads -system.physmem.totQLat 5746744750 # Total ticks spent queuing -system.physmem.totMemAccLat 8858644750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 829840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34625.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.364664 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.334270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.064891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6098 87.24% 87.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.37% 87.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 456 6.52% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 208 2.98% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 103 1.47% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 0.82% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.30% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.11% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads +system.physmem.totQLat 5731685000 # Total ticks spent queuing +system.physmem.totMemAccLat 8826260000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34728.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53375.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 475.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.27 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 475.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53478.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 473.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 328.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 473.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 328.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 145973 # Number of row buffer hits during reads -system.physmem.writeRowHits 82020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.73 # Row buffer hit rate for writes -system.physmem.avgGap 79753.58 # Average gap between requests -system.physmem.pageHitRate 81.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190882440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 104152125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640161600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6647542920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7581572250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16993287015 # Total energy per rank (pJ) -system.physmem_0.averagePower 760.170138 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12528806000 # Time in different power states -system.physmem_0.memoryStateTime::REF 746460000 # Time in different power states +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 145441 # Number of row buffer hits during reads +system.physmem.writeRowHits 81669 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.38 # Row buffer hit rate for writes +system.physmem.avgGap 79783.59 # Average gap between requests +system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190375920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103875750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 635356800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369036000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6553881090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7626357750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16934890590 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.674656 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12601715000 # Time in different power states +system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9079331500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8946212500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204271200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111457500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654100200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371699280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6857633520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7397282250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 17056519710 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.998761 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12224344750 # Time in different power states -system.physmem_1.memoryStateTime::REF 746460000 # Time in different power states +system.physmem_1.actEnergy 204815520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111754500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371893680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6747677955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7456388250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17000102385 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.598381 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12320846000 # Time in different power states +system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9383970250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9227273000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16500558 # Number of BP lookups -system.cpu.branchPred.condPredicted 10689411 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 329507 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9043813 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7288978 # Number of BTB hits +system.cpu.branchPred.lookups 16493971 # Number of BP lookups +system.cpu.branchPred.condPredicted 10685365 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 327092 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8977635 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7282355 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.596293 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1974529 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2931 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.116630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1973286 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2952 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22520885 # DTB read hits -system.cpu.dtb.read_misses 225850 # DTB read misses -system.cpu.dtb.read_acv 12 # DTB read access violations -system.cpu.dtb.read_accesses 22746735 # DTB read accesses -system.cpu.dtb.write_hits 15825785 # DTB write hits -system.cpu.dtb.write_misses 44675 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 15870460 # DTB write accesses -system.cpu.dtb.data_hits 38346670 # DTB hits -system.cpu.dtb.data_misses 270525 # DTB misses -system.cpu.dtb.data_acv 17 # DTB access violations -system.cpu.dtb.data_accesses 38617195 # DTB accesses -system.cpu.itb.fetch_hits 13761847 # ITB hits -system.cpu.itb.fetch_misses 29330 # ITB misses +system.cpu.dtb.read_hits 22518673 # DTB read hits +system.cpu.dtb.read_misses 225961 # DTB read misses +system.cpu.dtb.read_acv 15 # DTB read access violations +system.cpu.dtb.read_accesses 22744634 # DTB read accesses +system.cpu.dtb.write_hits 15824450 # DTB write hits +system.cpu.dtb.write_misses 44763 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15869213 # DTB write accesses +system.cpu.dtb.data_hits 38343123 # DTB hits +system.cpu.dtb.data_misses 270724 # DTB misses +system.cpu.dtb.data_acv 19 # DTB access violations +system.cpu.dtb.data_accesses 38613847 # DTB accesses +system.cpu.itb.fetch_hits 13750650 # ITB hits +system.cpu.itb.fetch_misses 29320 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13791177 # ITB accesses +system.cpu.itb.fetch_accesses 13779970 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,141 +324,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44713274 # number of cpu cycles simulated +system.cpu.numCycles 44593188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15584768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105191572 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16500558 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9263507 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27593237 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 896542 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 162 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 325871 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13761847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 191924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15564341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105145283 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16493971 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9255641 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27572822 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 891924 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 262 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 325760 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13750650 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190232 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43957183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.393046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43914039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.394343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.128103 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24416716 55.55% 55.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1522401 3.46% 59.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1379227 3.14% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1505485 3.42% 65.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4199085 9.55% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1828470 4.16% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669319 1.52% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1052182 2.39% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7384298 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24384273 55.53% 55.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1520929 3.46% 58.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1376099 3.13% 62.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1504413 3.43% 65.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4198532 9.56% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1828676 4.16% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 668520 1.52% 80.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050487 2.39% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7382110 16.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43957183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369030 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.352580 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14931500 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9767964 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18310970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 595597 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 351152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3708003 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98860 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103215952 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311866 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 351152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15279451 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4431592 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96231 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18542963 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5255794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102192828 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5698 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 95463 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 341437 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4753642 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61435412 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123253139 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122935807 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 317331 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43914039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369876 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.357878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14911775 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9756593 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18301996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 594945 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 348730 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3706760 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98994 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103174683 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312811 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 348730 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15258388 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4434115 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18534618 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5241400 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102158813 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5649 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94745 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 345515 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4735615 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61411273 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123213365 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122896091 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 317273 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8888531 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5692 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5745 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2361848 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23156457 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16385404 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1258348 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90834629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5552 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88691609 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70456 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11248424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4497706 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43957183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.017682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245665 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8864392 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5712 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5765 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2362727 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23149705 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16384887 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1256801 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 494099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90814957 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5561 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88678954 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70817 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11228761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4483589 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 978 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43914039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.019376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17476881 39.76% 39.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5730177 13.04% 52.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5107740 11.62% 64.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4380373 9.97% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4328154 9.85% 84.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2635103 5.99% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1947598 4.43% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378142 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 973015 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17441953 39.72% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5726957 13.04% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5104887 11.62% 64.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4381256 9.98% 74.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4320313 9.84% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2639459 6.01% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1947949 4.44% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1377906 3.14% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 973359 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43957183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43914039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243362 9.64% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1165216 46.16% 55.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1115524 44.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 242855 9.63% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1163309 46.14% 55.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1115010 44.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49430492 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43978 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49423838 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43986 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121147 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120628 0.14% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39084 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121174 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120676 0.14% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39089 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -481,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22917985 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16018139 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22912706 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16017331 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88691609 # Type of FU issued -system.cpu.iq.rate 1.983563 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2524102 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223325364 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101690449 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86898361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 609595 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 418176 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299341 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90910760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 304951 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1670602 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88678954 # Type of FU issued +system.cpu.iq.rate 1.988621 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2521174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028430 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223254204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101651163 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86893480 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 609734 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 418232 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299390 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90895107 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305021 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1671418 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2879819 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5660 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20258 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1772027 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2873067 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5610 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20361 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1771510 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3047 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205936 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3045 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 204833 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 351152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1286887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2706445 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100341607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125884 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23156457 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16385404 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5552 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3769 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2705021 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20258 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 121859 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 151192 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 273051 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87981340 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22747403 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 710269 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 348730 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1277507 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2721681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100319642 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124919 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23149705 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16384887 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5561 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3725 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2720217 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20361 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118662 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 150973 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 269635 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87973235 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22745315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 705719 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9501426 # number of nop insts executed -system.cpu.iew.exec_refs 38618193 # number of memory reference insts executed -system.cpu.iew.exec_branches 15127263 # Number of branches executed -system.cpu.iew.exec_stores 15870790 # Number of stores executed -system.cpu.iew.exec_rate 1.967678 # Inst execution rate -system.cpu.iew.wb_sent 87600358 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87197702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33849535 # num instructions producing a value -system.cpu.iew.wb_consumers 44277575 # num instructions consuming a value +system.cpu.iew.exec_nop 9499124 # number of nop insts executed +system.cpu.iew.exec_refs 38614853 # number of memory reference insts executed +system.cpu.iew.exec_branches 15126858 # Number of branches executed +system.cpu.iew.exec_stores 15869538 # Number of stores executed +system.cpu.iew.exec_rate 1.972795 # Inst execution rate +system.cpu.iew.wb_sent 87594856 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87192870 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33852684 # num instructions producing a value +system.cpu.iew.wb_consumers 44279326 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.950152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764485 # average fanout of values written-back +system.cpu.iew.wb_rate 1.955296 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764526 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8791000 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8765402 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 232388 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42666920 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.070472 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.884283 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 229860 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42628268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.072350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885151 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21190783 49.67% 49.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6285871 14.73% 64.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2905995 6.81% 71.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1744112 4.09% 75.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1680276 3.94% 79.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1128586 2.65% 81.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1203447 2.82% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 797041 1.87% 86.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5730809 13.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21157300 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6282680 14.74% 64.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2903206 6.81% 71.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1743375 4.09% 75.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1680050 3.94% 79.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1128930 2.65% 81.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1204133 2.82% 84.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 796945 1.87% 86.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5731649 13.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42666920 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42628268 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,333 +603,339 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5730809 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132750441 # The number of ROB reads -system.cpu.rob.rob_writes 195556891 # The number of ROB writes -system.cpu.timesIdled 46372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 756091 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5731649 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132685351 # The number of ROB reads +system.cpu.rob.rob_writes 195501271 # The number of ROB writes +system.cpu.timesIdled 46319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 679149 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.561783 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561783 # CPI: Total CPI of All Threads -system.cpu.ipc 1.780048 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.780048 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116466074 # number of integer regfile reads -system.cpu.int_regfile_writes 57713698 # number of integer regfile writes -system.cpu.fp_regfile_reads 255059 # number of floating regfile reads -system.cpu.fp_regfile_writes 240376 # number of floating regfile writes -system.cpu.misc_regfile_reads 38265 # number of misc regfile reads +system.cpu.cpi 0.560274 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.560274 # CPI: Total CPI of All Threads +system.cpu.ipc 1.784841 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.784841 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116453986 # number of integer regfile reads +system.cpu.int_regfile_writes 57709287 # number of integer regfile writes +system.cpu.fp_regfile_reads 255067 # number of floating regfile reads +system.cpu.fp_regfile_writes 240450 # number of floating regfile writes +system.cpu.misc_regfile_reads 38270 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201297 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.745765 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33997888 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205393 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.526031 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 229746500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.745765 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993834 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993834 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201399 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.676822 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33995451 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205495 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.432011 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.676822 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993818 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993818 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2788 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1232 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2778 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70843209 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70843209 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20436554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20436554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561278 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561278 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33997832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33997832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33997832 # number of overall hits -system.cpu.dcache.overall_hits::total 33997832 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268921 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268921 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052099 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321020 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321020 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321020 # number of overall misses -system.cpu.dcache.overall_misses::total 1321020 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17355062000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17355062000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89131929604 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89131929604 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106486991604 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106486991604 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106486991604 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106486991604 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20705475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20705475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70838999 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70838999 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20434147 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20434147 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561246 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561246 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 58 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33995393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33995393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33995393 # number of overall hits +system.cpu.dcache.overall_hits::total 33995393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269170 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052131 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052131 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321301 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321301 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321301 # number of overall misses +system.cpu.dcache.overall_misses::total 1321301 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17282869000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17282869000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89120990413 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89120990413 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106403859413 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106403859413 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106403859413 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106403859413 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20703317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20703317 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35318852 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35318852 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35318852 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35318852 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012988 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012988 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071996 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071996 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037403 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037403 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037403 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037403 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64535.912034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64535.912034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84718.196295 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84718.196295 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80609.674043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80609.674043 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6869550 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35316694 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35316694 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35316694 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35316694 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071998 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071998 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037413 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037413 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037413 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037413 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80529.613928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80529.613928 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6870751 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88969 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 89149 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.212849 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.070421 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168788 # number of writebacks -system.cpu.dcache.writebacks::total 168788 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206925 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206925 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908702 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908702 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205393 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205393 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205393 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205393 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3212836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3212836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14233206202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14233206202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17446042702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17446042702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17446042702 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17446042702 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005815 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005815 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51823.286986 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51823.286986 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99257.349889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99257.349889 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168802 # number of writebacks +system.cpu.dcache.writebacks::total 168802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207068 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207068 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908738 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908738 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115806 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240616218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240616218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17439107718 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17439107718 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17439107718 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17439107718 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 91498 # number of replacements -system.cpu.icache.tags.tagsinuse 1915.935564 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13655300 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93546 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 145.974173 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18815415500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1915.935564 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935515 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935515 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1476 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1477 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 380 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27617236 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27617236 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13655300 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13655300 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13655300 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13655300 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13655300 # number of overall hits -system.cpu.icache.overall_hits::total 13655300 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106545 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106545 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106545 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106545 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106545 # number of overall misses -system.cpu.icache.overall_misses::total 106545 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2015171999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2015171999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2015171999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2015171999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2015171999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2015171999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13761845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13761845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13761845 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13761845 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13761845 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13761845 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18913.811056 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18913.811056 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18913.811056 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18913.811056 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18913.811056 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18913.811056 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1468 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27594820 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27594820 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13644579 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13644579 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13644579 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13644579 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13644579 # number of overall hits +system.cpu.icache.overall_hits::total 13644579 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106069 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106069 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106069 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106069 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106069 # number of overall misses +system.cpu.icache.overall_misses::total 106069 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1942429499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1942429499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1942429499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1942429499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1942429499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1942429499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13750648 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13750648 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13750648 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13750648 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13750648 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13750648 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007714 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007714 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007714 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007714 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007714 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007714 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18312.885942 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18312.885942 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18312.885942 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18312.885942 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18312.885942 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18312.885942 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1399 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 77.263158 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 99.928571 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12998 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12998 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12998 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12998 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12998 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12998 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93547 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93547 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93547 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93547 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93547 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93547 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1645041500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1645041500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1645041500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1645041500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1645041500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1645041500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006798 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006798 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006798 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006798 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17585.187125 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17585.187125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17585.187125 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17585.187125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17585.187125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17585.187125 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 91476 # number of writebacks +system.cpu.icache.writebacks::total 91476 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12544 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12544 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12544 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12544 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12544 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12544 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93525 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93525 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93525 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93525 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93525 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93525 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1588807000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1588807000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1588807000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1588807000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1588807000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1588807000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006801 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006801 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006801 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006801 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006801 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006801 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16988.045977 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16988.045977 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16988.045977 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16988.045977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16988.045977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16988.045977 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132064 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30597.382084 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 281892 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164129 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.717503 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 133079 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30599.466713 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 282960 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165171 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.713134 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26451.406117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2221.195572 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1924.780395 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.807233 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.058740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.933758 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32065 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3040 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28434 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5041408 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5041408 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 168788 # 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mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912022 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912022 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078773 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448785 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448785 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555208 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555208 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96141.704197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96141.704197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71321.278328 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71321.278328 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89063.996118 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89063.996118 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.068506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.551973 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.551973 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 591735 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 292795 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 591895 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 292875 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4047 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4047 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 93547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61994 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612083 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5986944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23947584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132064 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005561 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.074364 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 155625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 91476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 93525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278525 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 890914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11840000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23955008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35795008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133079 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 432099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009366 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.096323 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 719774 99.44% 99.44% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4025 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428052 99.06% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4047 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 140327982 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432099 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 556225500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 140299972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308097983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308258967 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35190 # Transaction distribution -system.membus.trans_dist::Writeback 114348 # Transaction distribution -system.membus.trans_dist::CleanEvict 15746 # Transaction distribution -system.membus.trans_dist::ReadExReq 130783 # Transaction distribution -system.membus.trans_dist::ReadExResp 130783 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35190 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462040 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34266 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114413 # Transaction distribution +system.membus.trans_dist::CleanEvict 14730 # Transaction distribution +system.membus.trans_dist::ReadExReq 130784 # Transaction distribution +system.membus.trans_dist::ReadExResp 130784 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34266 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459243 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 459243 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17885632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17885632 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296067 # Request fanout histogram +system.membus.snoop_fanout::samples 294193 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296067 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294193 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296067 # Request fanout histogram -system.membus.reqLayer0.occupancy 778875000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294193 # Request fanout histogram +system.membus.reqLayer0.occupancy 777045500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 857731250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 852834000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- |