diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/se/50.vortex/ref/alpha/tru64/o3-timing | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/o3-timing')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 1434 |
1 files changed, 798 insertions, 636 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 8eb5d8593..42c254d5a 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023932 # Number of seconds simulated -sim_ticks 23931821000 # Number of ticks simulated -final_tick 23931821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024943 # Number of seconds simulated +sim_ticks 24942850000 # Number of ticks simulated +final_tick 24942850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61921 # Simulator instruction rate (inst/s) -host_op_rate 61921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18618559 # Simulator tick rate (ticks/s) -host_mem_usage 281736 # Number of bytes of host memory used -host_seconds 1285.37 # Real time elapsed on the host +host_inst_rate 187895 # Simulator instruction rate (inst/s) +host_op_rate 187895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58883311 # Simulator tick rate (ticks/s) +host_mem_usage 236320 # Number of bytes of host memory used +host_seconds 423.60 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154048 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158657 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166313 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20474163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 424290655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 444764818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20474163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20474163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 304906175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 304906175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 304906175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20474163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 424290655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 749670992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166313 # Total number of read requests seen -system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280328 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644032 # Total number of bytes read from memory -system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 490496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153472 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296640 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296640 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158648 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166312 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114010 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114010 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19664794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 407069441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 426734234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19664794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19664794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 292534333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 292534333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 292534333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19664794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 407069441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 719268568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166312 # Total number of read requests seen +system.physmem.writeReqs 114010 # Total number of write requests seen +system.physmem.cpureqs 280322 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10643968 # Total number of bytes read from memory +system.physmem.bytesWritten 7296640 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10643968 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296640 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10321 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10258 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10114 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7276 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10055 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10323 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10639 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6990 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23931788000 # Total gap between requests +system.physmem.totGap 24942817000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166313 # Categorize read packet sizes +system.physmem.readPktSize::6 166312 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114015 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 67890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114010 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 73936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -146,66 +146,208 @@ system.physmem.wrQLenPdf::18 4957 # Wh system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 7245305500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9792324250 # Sum of mem lat for all requests -system.physmem.totBusLat 831555000 # Total cycles spent in databus access -system.physmem.totBankLat 1715463750 # Total cycles spent in bank access -system.physmem.avgQLat 43564.80 # Average queueing delay per request -system.physmem.avgBankLat 10314.79 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 49789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.286489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.159256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 741.433360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 20689 41.55% 41.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7785 15.64% 57.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4196 8.43% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3037 6.10% 71.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2069 4.16% 75.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1703 3.42% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1326 2.66% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1152 2.31% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 751 1.51% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 622 1.25% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 468 0.94% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 538 1.08% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 428 0.86% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 311 0.62% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 271 0.54% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 335 0.67% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 282 0.57% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 173 0.35% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 131 0.26% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 297 0.60% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 411 0.83% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 172 0.35% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 311 0.62% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 639 1.28% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 258 0.52% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 81 0.16% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 48 0.10% 97.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 163 0.33% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 101 0.20% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 35 0.07% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 33 0.07% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 83 0.17% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 54 0.11% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 28 0.06% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 37 0.07% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 43 0.09% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 20 0.04% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 23 0.05% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 20 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 10 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 11 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 8 0.02% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 16 0.03% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 8 0.02% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 7 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 10 0.02% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 8 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 8 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 6 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 8 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 9 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 10 0.02% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 165 0.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49789 # Bytes accessed per row activation +system.physmem.totQLat 6526905250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8951626500 # Sum of mem lat for all requests +system.physmem.totBusLat 831550000 # Total cycles spent in databus access +system.physmem.totBankLat 1593171250 # Total cycles spent in bank access +system.physmem.avgQLat 39245.42 # Average queueing delay per request +system.physmem.avgBankLat 9579.53 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58879.59 # Average memory access latency -system.physmem.avgRdBW 444.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 304.91 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 444.76 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 304.91 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53824.94 # Average memory access latency +system.physmem.avgRdBW 426.73 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 292.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 426.73 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 292.53 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.86 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 9.84 # Average write queue length over time -system.physmem.readRowHits 149147 # Number of row buffer hits during reads -system.physmem.writeRowHits 70867 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.16 # Row buffer hit rate for writes -system.physmem.avgGap 85370.67 # Average gap between requests -system.cpu.branchPred.lookups 16571170 # Number of BP lookups -system.cpu.branchPred.condPredicted 10694499 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11996955 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7368452 # Number of BTB hits +system.physmem.busUtil 5.62 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.36 # Average read queue length over time +system.physmem.avgWrQLen 10.09 # Average write queue length over time +system.physmem.readRowHits 154174 # Number of row buffer hits during reads +system.physmem.writeRowHits 76335 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.95 # Row buffer hit rate for writes +system.physmem.avgGap 88979.16 # Average gap between requests +system.membus.throughput 719268568 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35517 # Transaction distribution +system.membus.trans_dist::ReadResp 35517 # Transaction distribution +system.membus.trans_dist::Writeback 114010 # Transaction distribution +system.membus.trans_dist::ReadExReq 130795 # Transaction distribution +system.membus.trans_dist::ReadExResp 130795 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 446634 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 446634 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17940608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940608 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1221780000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 1527507000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.1 # Layer utilization (%) +system.cpu.branchPred.lookups 16555988 # Number of BP lookups +system.cpu.branchPred.condPredicted 10692092 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 419935 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11595461 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7351910 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.419352 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1995064 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41482 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.403344 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990234 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41425 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22414538 # DTB read hits -system.cpu.dtb.read_misses 219003 # DTB read misses -system.cpu.dtb.read_acv 44 # DTB read access violations -system.cpu.dtb.read_accesses 22633541 # DTB read accesses -system.cpu.dtb.write_hits 15711620 # DTB write hits -system.cpu.dtb.write_misses 41172 # DTB write misses +system.cpu.dtb.read_hits 22410816 # DTB read hits +system.cpu.dtb.read_misses 219473 # DTB read misses +system.cpu.dtb.read_acv 42 # DTB read access violations +system.cpu.dtb.read_accesses 22630289 # DTB read accesses +system.cpu.dtb.write_hits 15705108 # DTB write hits +system.cpu.dtb.write_misses 41065 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15752792 # DTB write accesses -system.cpu.dtb.data_hits 38126158 # DTB hits -system.cpu.dtb.data_misses 260175 # DTB misses -system.cpu.dtb.data_acv 46 # DTB access violations -system.cpu.dtb.data_accesses 38386333 # DTB accesses -system.cpu.itb.fetch_hits 13959521 # ITB hits -system.cpu.itb.fetch_misses 35718 # ITB misses +system.cpu.dtb.write_accesses 15746173 # DTB write accesses +system.cpu.dtb.data_hits 38115924 # DTB hits +system.cpu.dtb.data_misses 260538 # DTB misses +system.cpu.dtb.data_acv 44 # DTB access violations +system.cpu.dtb.data_accesses 38376462 # DTB accesses +system.cpu.itb.fetch_hits 13936543 # ITB hits +system.cpu.itb.fetch_misses 35109 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13995239 # ITB accesses +system.cpu.itb.fetch_accesses 13971652 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,139 +361,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 47863646 # number of cpu cycles simulated +system.cpu.numCycles 49885704 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15840434 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105551509 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16571170 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9363516 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19590320 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2026285 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6404003 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314524 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13959521 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209834 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43625903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.419469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.136822 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15828757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105472202 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16555988 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9342144 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19569330 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2015634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7564714 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 312127 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13936543 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44745227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.357172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120107 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24035583 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538195 3.53% 58.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1379254 3.16% 61.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510848 3.46% 65.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4145444 9.50% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1853786 4.25% 79.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 680324 1.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070140 2.45% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7412329 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25175897 56.26% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1533640 3.43% 59.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1372500 3.07% 62.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510966 3.38% 66.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4145174 9.26% 75.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1852523 4.14% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674526 1.51% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069811 2.39% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7410190 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43625903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346216 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.205254 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16922417 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5946391 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18583818 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 809277 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1364000 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3756330 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107588 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103803150 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305479 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1364000 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17385205 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3661755 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85469 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18882151 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2247323 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102504062 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 474 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2634 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2121433 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61730148 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123523109 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123071072 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 452037 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44745227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.331878 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.114277 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16915257 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7099488 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18565359 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 807394 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1357729 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3748109 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107416 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103728039 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1357729 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17378057 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4787405 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18857243 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2280087 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102449322 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 562 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2762 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2150788 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61699088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123470125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123020099 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 450026 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9183267 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5533 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4628434 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23258454 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16285736 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1194307 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 458239 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90833658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5326 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88506663 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 99992 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10775029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4713260 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43625903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.028764 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109591 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9152207 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5534 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4701242 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23248702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16281518 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1196604 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 458974 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90797694 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5272 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88473068 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 98121 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10747304 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4709427 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 689 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44745227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.977263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106527 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15319091 35.11% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6943764 15.92% 51.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5619916 12.88% 63.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4753240 10.90% 74.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4687288 10.74% 85.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2648310 6.07% 91.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1927283 4.42% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1307141 3.00% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 419870 0.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16442789 36.75% 36.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6947095 15.53% 52.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5617294 12.55% 64.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4751397 10.62% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4688341 10.48% 85.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649423 5.92% 91.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1924303 4.30% 96.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1305783 2.92% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 418802 0.94% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43625903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44745227 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126036 6.75% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 786436 42.09% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 955888 51.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126164 6.77% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785807 42.18% 48.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 951202 51.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49401565 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43900 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49382358 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43890 0.05% 55.87% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121291 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121091 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38958 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121219 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121003 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -373,84 +515,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22873159 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15906558 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22865563 25.84% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15899938 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88506663 # Type of FU issued -system.cpu.iq.rate 1.849142 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1868360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021110 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222003769 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101216135 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86588999 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603812 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415953 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90073048 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301975 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1468681 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88473068 # Type of FU issued +system.cpu.iq.rate 1.773515 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1863173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021059 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223048793 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101154216 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86567905 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603864 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414189 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294216 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90034241 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302000 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467603 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2981816 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4834 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18324 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1672359 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2972064 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5071 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1668141 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2816 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2922 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100269 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1364000 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2689383 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74209 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100326423 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 230599 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23258454 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16285736 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5326 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60174 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 487 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18324 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 205931 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 367046 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87639637 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22636834 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 867026 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1357729 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3744152 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 78814 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100285943 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 219681 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23248702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16281518 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5272 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60147 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 593 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 199378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160408 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359786 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87617560 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22633363 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 855508 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9487439 # number of nop insts executed -system.cpu.iew.exec_refs 38389952 # number of memory reference insts executed -system.cpu.iew.exec_branches 15091410 # Number of branches executed -system.cpu.iew.exec_stores 15753118 # Number of stores executed -system.cpu.iew.exec_rate 1.831027 # Inst execution rate -system.cpu.iew.wb_sent 87274889 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86883155 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33355142 # num instructions producing a value -system.cpu.iew.wb_consumers 43763107 # num instructions consuming a value +system.cpu.iew.exec_nop 9482977 # number of nop insts executed +system.cpu.iew.exec_refs 38379854 # number of memory reference insts executed +system.cpu.iew.exec_branches 15087965 # Number of branches executed +system.cpu.iew.exec_stores 15746491 # Number of stores executed +system.cpu.iew.exec_rate 1.756366 # Inst execution rate +system.cpu.iew.wb_sent 87252732 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86862121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33357056 # num instructions producing a value +system.cpu.iew.wb_consumers 43763173 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.815222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762175 # average fanout of values written-back +system.cpu.iew.wb_rate 1.741223 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762217 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8976597 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8947131 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 322215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42261903 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.090315 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.803165 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 315269 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43387498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.036086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.786442 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19374336 45.84% 45.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7031479 16.64% 62.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3426891 8.11% 70.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2063946 4.88% 75.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2064090 4.88% 80.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1160431 2.75% 83.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1098411 2.60% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 723960 1.71% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5318359 12.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20491808 47.23% 47.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7040185 16.23% 63.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3430647 7.91% 71.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2065344 4.76% 76.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2060078 4.75% 80.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1160326 2.67% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1096269 2.53% 86.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719123 1.66% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5323718 12.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42261903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43387498 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +603,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5318359 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5323718 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132943471 # The number of ROB reads -system.cpu.rob.rob_writes 196001226 # The number of ROB writes -system.cpu.timesIdled 70501 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4237743 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 134034241 # The number of ROB reads +system.cpu.rob.rob_writes 195936054 # The number of ROB writes +system.cpu.timesIdled 84426 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5140477 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.601364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.601364 # CPI: Total CPI of All Threads -system.cpu.ipc 1.662885 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.662885 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115989230 # number of integer regfile reads -system.cpu.int_regfile_writes 57546941 # number of integer regfile writes -system.cpu.fp_regfile_reads 249538 # number of floating regfile reads -system.cpu.fp_regfile_writes 239891 # number of floating regfile writes -system.cpu.misc_regfile_reads 38020 # number of misc regfile reads +system.cpu.cpi 0.626770 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.626770 # CPI: Total CPI of All Threads +system.cpu.ipc 1.595482 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.595482 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115957750 # number of integer regfile reads +system.cpu.int_regfile_writes 57532597 # number of integer regfile writes +system.cpu.fp_regfile_reads 249573 # number of floating regfile reads +system.cpu.fp_regfile_writes 239887 # number of floating regfile writes +system.cpu.misc_regfile_reads 38017 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91116 # number of replacements -system.cpu.icache.tagsinuse 1928.908016 # Cycle average of tags in use -system.cpu.icache.total_refs 13854125 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93164 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 148.706850 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19689670000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1928.908016 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941850 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941850 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13854125 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13854125 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13854125 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13854125 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13854125 # number of overall hits -system.cpu.icache.overall_hits::total 13854125 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105395 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105395 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105395 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105395 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105395 # number of overall misses -system.cpu.icache.overall_misses::total 105395 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863166499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1863166499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1863166499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1863166499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1863166499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1863166499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13959520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13959520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13959520 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13959520 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13959520 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13959520 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007550 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007550 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007550 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007550 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007550 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007550 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.940120 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17677.940120 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17677.940120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17677.940120 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 817 # number of cycles access was blocked +system.cpu.toL2Bus.throughput 1201112463 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155760 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143412 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 187195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580089 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 767284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5990208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23968960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29959168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29959168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 402997500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 140404482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 308361998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.icache.replacements 91549 # number of replacements +system.cpu.icache.tagsinuse 1926.731072 # Cycle average of tags in use +system.cpu.icache.total_refs 13830286 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93597 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.764202 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20183588000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1926.731072 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.940787 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.940787 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13830286 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13830286 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13830286 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13830286 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13830286 # number of overall hits +system.cpu.icache.overall_hits::total 13830286 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106255 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106255 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106255 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106255 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106255 # number of overall misses +system.cpu.icache.overall_misses::total 106255 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2059581499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2059581499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2059581499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2059581499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2059581499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2059581499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13936541 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13936541 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13936541 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13936541 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13936541 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13936541 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007624 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007624 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007624 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007624 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007624 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007624 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19383.384302 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19383.384302 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19383.384302 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19383.384302 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 622 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.357143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.428571 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12230 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12230 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12230 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12230 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12230 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12230 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93165 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93165 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93165 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93165 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93165 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93165 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1451229000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1451229000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1451229000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1451229000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1451229000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1451229000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006674 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006674 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006674 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006674 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006674 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006674 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15576.976332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15576.976332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15576.976332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15576.976332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15576.976332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15576.976332 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12657 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12657 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12657 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12657 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12657 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12657 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93598 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93598 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93598 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93598 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93598 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93598 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1582060018 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1582060018 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1582060018 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1582060018 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1582060018 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1582060018 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006716 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006716 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006716 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16902.711789 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16902.711789 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16902.711789 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16902.711789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16902.711789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16902.711789 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 132410 # number of replacements -system.cpu.l2cache.tagsinuse 30827.017190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 159549 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 164472 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.970068 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132411 # number of replacements +system.cpu.l2cache.tagsinuse 30722.304633 # Cycle average of tags in use +system.cpu.l2cache.total_refs 159968 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164470 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.972627 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26661.032044 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2123.232682 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2042.752464 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813630 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.064796 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.062340 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.940766 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85508 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34321 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 119829 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168939 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168939 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12609 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12609 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85508 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46930 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132438 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85508 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46930 # number of overall hits -system.cpu.l2cache.overall_hits::total 132438 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7657 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27859 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081893 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771732 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555911 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081893 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771732 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555911 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69542.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63490.844792 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64796.905794 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94778.416606 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94778.416606 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69542.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89285.421184 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88375.529874 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69542.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89285.421184 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88375.529874 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201491 # number of replacements -system.cpu.dcache.tagsinuse 4076.541723 # Cycle average of tags in use -system.cpu.dcache.total_refs 34211115 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205587 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.406996 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 178802000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.541723 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995249 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20636989 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20636989 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574068 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574068 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 58 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34211057 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34211057 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34211057 # number of overall hits -system.cpu.dcache.overall_hits::total 34211057 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039309 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039309 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306495 # number of overall misses -system.cpu.dcache.overall_misses::total 1306495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12035490500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12035490500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 79072087779 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 79072087779 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91107578279 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91107578279 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91107578279 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91107578279 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20904175 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20904175 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201478 # number of replacements +system.cpu.dcache.tagsinuse 4074.502987 # Cycle average of tags in use +system.cpu.dcache.total_refs 34204494 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205574 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.385311 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 214402000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4074.502987 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994752 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994752 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20630348 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20630348 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574089 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574089 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34204437 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34204437 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34204437 # number of overall hits +system.cpu.dcache.overall_hits::total 34204437 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 266891 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 266891 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039288 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039288 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306179 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306179 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306179 # number of overall misses +system.cpu.dcache.overall_misses::total 1306179 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15635191500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15635191500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89961325949 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89961325949 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105596517449 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105596517449 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105596517449 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105596517449 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20897239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20897239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35517552 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35517552 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35517552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35517552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012781 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012781 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036784 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036784 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036784 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036784 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45045.363530 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45045.363530 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76081.403874 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76081.403874 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69734.348986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69734.348986 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4381626 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112316 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35510616 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35510616 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35510616 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35510616 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012772 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012772 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071119 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071119 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036783 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036783 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036783 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036783 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58582.685441 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58582.685441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86560.535625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 86560.535625 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80843.833387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80843.833387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5220473 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 159 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112927 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.011592 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.228741 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 159 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168939 # number of writebacks -system.cpu.dcache.writebacks::total 168939 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205002 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205002 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895906 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895906 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100908 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100908 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100908 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100908 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62184 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62184 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143403 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143403 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205587 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205587 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205587 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205587 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2020761500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2020761500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12440224991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12440224991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14460986491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14460986491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14460986491 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14460986491 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168941 # number of writebacks +system.cpu.dcache.writebacks::total 168941 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204728 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204728 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895877 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895877 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100605 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100605 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100605 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100605 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62163 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62163 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143411 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143411 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205574 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205574 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205574 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205574 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2517427002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2517427002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14256184493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14256184493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16773611495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16773611495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16773611495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16773611495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005788 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005788 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32496.486234 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32496.486234 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86750.102794 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86750.102794 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40497.192896 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40497.192896 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99407.887073 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99407.887073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |