diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-19 04:06:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-19 04:06:21 -0400 |
| commit | f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (patch) | |
| tree | aac69ab2cec4c10204cfc44af082722a3ed98792 /tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic | |
| parent | 877435950ca2dfb7213dc502e7d9e8374e55e16b (diff) | |
| download | gem5-f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17.tar.xz | |
tests: Recategorise regressions based on run time
This patch takes a first stab at recategorising the regression tests
based on actual run times. The simple-atomic and simple-timing runs of
vortex and twolf all finish in less than 180 s, and they are
consequently moved from long to quick. All realview64 linux-boot
regressions take more than 700 s, and they are therefore moved to
long.
Later patches will rename quick to short, and further divide the
regressions into short, medium and long.
--HG--
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/smred.out
rename : tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/se/50.vortex/test.py => tests/quick/se/50.vortex/test.py
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
rename : tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
rename : tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
rename : tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
rename : tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/se/70.twolf/test.py => tests/quick/se/70.twolf/test.py
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic')
6 files changed, 0 insertions, 756 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index bc26b879f..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,172 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 506aa6e28..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index faff61794..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,11 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 18:27:58 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 44221003000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index db2ebe7dc..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2813944 # Simulator instruction rate (inst/s) -host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1408584494 # Simulator tick rate (ticks/s) -host_mem_usage 287952 # Number of bytes of host memory used -host_seconds 31.39 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory -system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory -system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 108714711 # Transaction distribution -system.membus.trans_dist::ReadResp 108714711 # Transaction distribution -system.membus.trans_dist::WriteReq 14613377 # Transaction distribution -system.membus.trans_dist::WriteResp 14613377 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 123328088 # Request fanout histogram -system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram -system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 123328088 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438073 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442007 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 88442007 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction - ----------- End Simulation Statistics ---------- |