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authorAndreas Hansson <andreas.hansson@arm.com>2013-06-27 05:49:51 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-06-27 05:49:51 -0400
commit5a15909bac241dc795c691d49c4e2c68cab745f4 (patch)
treed0ae694e320c725ed8116943c7179516567279f3 /tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
parentac515d7a9b131ffc9e128bd209fcddb2f383808b (diff)
downloadgem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt62
1 files changed, 31 insertions, 31 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 9b4737e22..060f66d07 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 267269454 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.replacements 74391 # number of replacements
-system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use
-system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 74391 # number of replacements
+system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits
@@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 131235 # number of replacements
-system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 163291 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.869760 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.937769 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements 131235 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits
@@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 200248 # number of replacements
-system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use
-system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 200248 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits