diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/50.vortex/ref/alpha/tru64/simple-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/simple-timing')
3 files changed, 259 insertions, 181 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index f99b5fb55..4c4894527 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index e74b48d2a..471c7b55a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 05:42:49 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:25:32 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 59b869a9f..c906eecdf 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.134277 # Nu sim_ticks 134276988000 # Number of ticks simulated final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1801981 # Simulator instruction rate (inst/s) -host_tick_rate 2738992827 # Simulator tick rate (ticks/s) -host_mem_usage 215584 # Number of bytes of host memory used -host_seconds 49.02 # Real time elapsed on the host +host_inst_rate 2261546 # Simulator instruction rate (inst/s) +host_op_rate 2261545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3437525661 # Simulator tick rate (ticks/s) +host_mem_usage 217500 # Number of bytes of host memory used +host_seconds 39.06 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated +sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read 11121920 # Number of bytes read from this memory system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory system.physmem.bytes_written 7712384 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4583 # Nu system.cpu.numCycles 268553976 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 88340673 # Number of instructions executed +system.cpu.committedInsts 88340673 # Number of instructions committed +system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses system.cpu.num_func_calls 3321606 # number of times a function call or return occured @@ -79,26 +82,39 @@ system.cpu.icache.total_refs 88361638 # To system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses -system.cpu.icache.overall_misses 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1436470000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 18793.107960 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1871.404551 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913772 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913772 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits +system.cpu.icache.overall_hits::total 88361638 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses +system.cpu.icache.overall_misses::total 76436 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1436470000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1436470000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1436470000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1436470000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1436470000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1436470000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 1207162000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1207162000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1207162000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1207162000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1207162000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use @@ -134,32 +148,49 @@ system.cpu.dcache.total_refs 34685671 # To system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4078.858373 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995815 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9793210000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 47925.116470 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4078.858373 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits +system.cpu.dcache.overall_hits::total 34685671 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses +system.cpu.dcache.overall_misses::total 204344 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2261000000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2261000000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7532210000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7532210000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9793210000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9793210000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9793210000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9793210000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161222 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2078702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 7101476000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9180178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9180178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 161222 # number of writebacks +system.cpu.dcache.writebacks::total 161222 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7101476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7101476000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9180178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 147405 # number of replacements system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use @@ -199,36 +232,75 @@ system.cpu.l2cache.total_refs 122958 # To system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 107000 # number of overall hits -system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 173780 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15808.263557 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12099 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 67713 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39287 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 107000 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 67713 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39287 # number of overall hits +system.cpu.l2cache.overall_hits::total 107000 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 8723 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 42301 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131479 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131479 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 8723 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165057 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 173780 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8723 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165057 # number of overall misses +system.cpu.l2cache.overall_misses::total 173780 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 453596000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1746056000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2199652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6836908000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6836908000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 453596000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8582964000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9036560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 453596000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8582964000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9036560000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161222 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161222 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,30 +309,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120506 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks +system.cpu.l2cache.writebacks::total 120506 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131479 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8723 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165057 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 173780 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8723 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165057 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 173780 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 348920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1692040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5259160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |