stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 41 insertions, 5 deletions

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index a53da63fa..9b4737e22 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.133635                       # Nu
 sim_ticks                                133634727000                       # Number of ticks simulated
 final_tick                               133634727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 996502                       # Simulator instruction rate (inst/s)
-host_op_rate                                   996501                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1507427540                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280652                       # Number of bytes of host memory used
-host_seconds                                    88.65                       # Real time elapsed on the host
+host_inst_rate                                 671194                       # Simulator instruction rate (inst/s)
+host_op_rate                                   671194                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1015328507                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233108                       # Number of bytes of host memory used
+host_seconds                                   131.62                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            432896                       # Number of bytes read from this memory
@@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks          54587966                       # To
 system.physmem.bw_total::cpu.inst             3239397                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            75855253                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              133682617                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                    133682617                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               34272                       # Transaction distribution
+system.membus.trans_dist::ReadResp              34272                       # Transaction distribution
+system.membus.trans_dist::Writeback            113982                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130881                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130881                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side       444288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count                        444288                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side     17864640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size                   17864640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               17864640                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          1190991000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1486377000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               215108158                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         137202                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        137202                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168375                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143578                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143578                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side       152872                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side       577063                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                   729935                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side      4891904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side     23854016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size              28745920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          28745920                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      392952500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     114654000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     306516000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------