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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/50.vortex/ref/alpha/tru64/simple-timing | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/simple-timing')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 005dec492..beac32b45 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1051168 # Simulator instruction rate (inst/s) -host_op_rate 1051168 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1590122468 # Simulator tick rate (ticks/s) -host_mem_usage 273520 # Number of bytes of host memory used -host_seconds 84.04 # Real time elapsed on the host +host_inst_rate 1560477 # Simulator instruction rate (inst/s) +host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2360564466 # Simulator tick rate (ticks/s) +host_mem_usage 272464 # Number of bytes of host memory used +host_seconds 56.61 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -110,10 +110,10 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction |