diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:56 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:56 -0400 |
| commit | 351e146b37c61481152ef3ad551b2dd30aa6127a (patch) | |
| tree | c3efe5e53ccfe3c0d30718b599b5f6c3972f5e3a /tests/long/se/50.vortex/ref/alpha/tru64 | |
| parent | 83a46bfc09cbfd8b7e117fc7bdb14ad907438f6f (diff) | |
| download | gem5-351e146b37c61481152ef3ad551b2dd30aa6127a.tar.xz | |
alpha: Stop using 'inorder' and rely entirely on 'minor'
This patch avoids building the 'inorder' CPU model for any permutation
of ALPHA, and also removes the ALPHA regressions using the 'inorder'
CPU. The 'minor' CPU is already providing a broader test coverage.
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64')
6 files changed, 0 insertions, 1532 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini deleted file mode 100644 index 7b7e53586..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ /dev/null @@ -1,346 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=InOrderCPU -children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -activity=0 -branchPred=system.cpu.branchPred -cachePorts=2 -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBuffSize=4 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -stageTracing=false -stageWidth=4 -switched_out=false -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentBus -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentBus -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=DRAMCtrl -activation_limit=4 -addr_mapping=RoRaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCK=1250 -tCL=13750 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr deleted file mode 100755 index de77515a1..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout deleted file mode 100755 index 46359a0c9..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ /dev/null @@ -1,11 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 18:16:43 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 43690025000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt deleted file mode 100644 index ca907eb24..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ /dev/null @@ -1,754 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.043473 # Number of seconds simulated -sim_ticks 43472869000 # Number of ticks simulated -final_tick 43472869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112027 # Simulator instruction rate (inst/s) -host_op_rate 112027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55129043 # Simulator tick rate (ticks/s) -host_mem_usage 274568 # Number of bytes of host memory used -host_seconds 788.57 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory -system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7103 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory -system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10456913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 233211385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 243668298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10456913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10456913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 167824396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 167824396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 167824396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10456913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 233211385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 411492694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165515 # Number of read requests accepted -system.physmem.writeReqs 113997 # Number of write requests accepted -system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10592320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 7293824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10379 # Per bank write bursts -system.physmem.perBankRdBursts::1 10436 # Per bank write bursts -system.physmem.perBankRdBursts::2 10256 # Per bank write bursts -system.physmem.perBankRdBursts::3 10015 # Per bank write bursts -system.physmem.perBankRdBursts::4 10350 # Per bank write bursts -system.physmem.perBankRdBursts::5 10362 # Per bank write bursts -system.physmem.perBankRdBursts::6 9796 # Per bank write bursts -system.physmem.perBankRdBursts::7 10273 # Per bank write bursts -system.physmem.perBankRdBursts::8 10509 # Per bank write bursts -system.physmem.perBankRdBursts::9 10590 # Per bank write bursts -system.physmem.perBankRdBursts::10 10475 # Per bank write bursts -system.physmem.perBankRdBursts::11 10188 # Per bank write bursts -system.physmem.perBankRdBursts::12 10235 # Per bank write bursts -system.physmem.perBankRdBursts::13 10580 # Per bank write bursts -system.physmem.perBankRdBursts::14 10468 # Per bank write bursts -system.physmem.perBankRdBursts::15 10593 # Per bank write bursts -system.physmem.perBankWrBursts::0 7081 # Per bank write bursts -system.physmem.perBankWrBursts::1 7259 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts -system.physmem.perBankWrBursts::4 7125 # Per bank write bursts -system.physmem.perBankWrBursts::5 7170 # Per bank write bursts -system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 7083 # Per bank write bursts -system.physmem.perBankWrBursts::8 7217 # Per bank write bursts -system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7081 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6963 # Per bank write bursts -system.physmem.perBankWrBursts::13 7284 # Per bank write bursts -system.physmem.perBankWrBursts::14 7282 # Per bank write bursts -system.physmem.perBankWrBursts::15 7472 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 43472848000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165515 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 113997 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 70302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52007 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.898321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.122220 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.471226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18183 34.96% 34.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10752 20.67% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5531 10.64% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3167 6.09% 72.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2729 5.25% 77.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1801 3.46% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1676 3.22% 84.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1325 2.55% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6843 13.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52007 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.806818 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 349.983272 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6951 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6952 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.395339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.363988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.079809 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5950 85.60% 85.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.50% 86.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 555 7.98% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 213 3.06% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 101 1.45% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.81% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 23 0.33% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 12 0.17% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6951 # Writes before turning the bus around for reads -system.physmem.totQLat 4829573500 # Total ticks spent queuing -system.physmem.totMemAccLat 7932792250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827525000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29180.83 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47930.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 243.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 167.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 243.67 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 167.82 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.busUtilRead 1.90 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 145183 # Number of row buffer hits during reads -system.physmem.writeRowHits 82273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.17 # Row buffer hit rate for writes -system.physmem.avgGap 155531.24 # Average gap between requests -system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 26086323250 # Time in different power states -system.physmem.memoryStateTime::REF 1451580000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15933004250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 411492694 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 34625 # Transaction distribution -system.membus.trans_dist::ReadResp 34625 # Transaction distribution -system.membus.trans_dist::Writeback 113997 # Transaction distribution -system.membus.trans_dist::ReadExReq 130890 # Transaction distribution -system.membus.trans_dist::ReadExResp 130890 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 445027 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17888768 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17888768 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1219071000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1523545750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18742718 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318358 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507357 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4664025 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076208 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277728 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367876 # DTB read accesses -system.cpu.dtb.write_hits 14728971 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736223 # DTB write accesses -system.cpu.dtb.data_hits 35006699 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104099 # DTB accesses -system.cpu.itb.fetch_hits 12367762 # ITB hits -system.cpu.itb.fetch_misses 11021 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378783 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 86945739 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8074236 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668482 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74162124 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481374 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174248 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060070 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77212885 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 241035 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17370075 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575664 # Number of cycles cpu stages are processed. -system.cpu.activity 80.021936 # Percentage of cycles cpu is active -system.cpu.comLoads 20276638 # Number of Load instructions committed -system.cpu.comStores 14613377 # Number of Store instructions committed -system.cpu.comBranches 13754477 # Number of Branches instructions committed -system.cpu.comNops 8748916 # Number of Nop instructions committed -system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed -system.cpu.comInts 30791227 # Number of Integer instructions committed -system.cpu.comFloats 151453 # Number of Floating Point instructions committed -system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.984210 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.984210 # CPI: Total CPI of All Threads -system.cpu.ipc 1.016044 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.016044 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34290146 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655593 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.561442 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44490597 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455142 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.829468 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 43915285 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030454 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.491159 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 64825125 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120614 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.441861 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40903528 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46042211 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.955109 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.099937 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250492 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760209 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.099937 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930713 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930713 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24821923 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24821923 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 12250492 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250492 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250492 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250492 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250492 # number of overall hits -system.cpu.icache.overall_hits::total 12250492 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117261 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117261 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117261 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117261 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117261 # number of overall misses -system.cpu.icache.overall_misses::total 117261 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1989588981 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1989588981 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1989588981 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1989588981 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1989588981 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1989588981 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367753 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367753 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367753 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367753 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367753 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367753 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009481 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009481 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009481 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009481 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009481 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009481 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16967.184153 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16967.184153 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16967.184153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16967.184153 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.133333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30844 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30844 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30844 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30844 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30844 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30844 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1409598264 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1409598264 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1409598264 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1409598264 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1409598264 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1409598264 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16311.585267 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16311.585267 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 675902573 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 130854736 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326587968 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30879.620467 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27087.517417 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.809532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1783.293518 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.826645 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061304 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054422 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.942371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17062 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13579 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3980348 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3980348 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125249 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits -system.cpu.l2cache.overall_hits::total 125249 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130890 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130890 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165515 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses -system.cpu.l2cache.overall_misses::total 165515 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 527407000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2000529000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2527936000 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74251.302267 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72688.358404 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73008.981949 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98232.112843 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98232.112843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 92955.546325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 92955.546325 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks -system.cpu.l2cache.writebacks::total 113997 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7103 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27522 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34625 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130890 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130890 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165515 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 438280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1653149000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2091429000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11252735250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11252735250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12905884250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13344164250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12905884250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13344164250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61703.505561 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60066.455926 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60402.281588 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85970.931698 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85970.931698 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200251 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.191917 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33755204 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.185709 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 301118000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.191917 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995164 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995164 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3099 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984377 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20180307 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180307 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574897 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574897 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33755204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33755204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33755204 # number of overall hits -system.cpu.dcache.overall_hits::total 33755204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96331 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96331 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038480 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038480 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1134811 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1134811 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1134811 # number of overall misses -system.cpu.dcache.overall_misses::total 1134811 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5018382484 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5018382484 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 82442485122 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 82442485122 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 87460867606 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 87460867606 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 87460867606 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 87460867606 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071064 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071064 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032525 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032525 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032525 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032525 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52095.197641 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52095.197641 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79387.648411 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79387.648411 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77070.866960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77070.866960 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5473044 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.883943 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks -system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 894900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 894900 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930464 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930464 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930464 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930464 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395231766 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395231766 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13128048266 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13128048266 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15523280032 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15523280032 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15523280032 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15523280032 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39416.653216 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39416.653216 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91433.683424 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91433.683424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- |