diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/50.vortex/ref/alpha/tru64 | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt | 1138 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 1624 |
2 files changed, 1385 insertions, 1377 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 6234d30e2..58628a22b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060001 # Number of seconds simulated -sim_ticks 60000593000 # Number of ticks simulated -final_tick 60000593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060094 # Number of seconds simulated +sim_ticks 60093931000 # Number of ticks simulated +final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262235 # Simulator instruction rate (inst/s) -host_op_rate 262235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177912819 # Simulator tick rate (ticks/s) -host_mem_usage 257844 # Number of bytes of host memory used -host_seconds 337.25 # Real time elapsed on the host +host_inst_rate 276952 # Simulator instruction rate (inst/s) +host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188189933 # Simulator tick rate (ticks/s) +host_mem_usage 264524 # Number of bytes of host memory used +host_seconds 319.33 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 433344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10150272 # Number of bytes read from this memory -system.physmem.bytes_read::total 10583616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7325952 # Number of bytes written to this memory -system.physmem.bytes_written::total 7325952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158598 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165369 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114468 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114468 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7222329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169169528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176391857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122097993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7222329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169169528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 298489850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165369 # Number of read requests accepted -system.physmem.writeReqs 114468 # Number of write requests accepted -system.physmem.readBursts 165369 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114468 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10583232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7324288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10583616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7325952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165736 # Number of read requests accepted +system.physmem.writeReqs 115250 # Number of write requests accepted +system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10322 # Per bank write bursts -system.physmem.perBankRdBursts::1 10363 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10055 # Per bank write bursts -system.physmem.perBankRdBursts::4 10347 # Per bank write bursts -system.physmem.perBankRdBursts::5 10343 # Per bank write bursts -system.physmem.perBankRdBursts::6 9774 # Per bank write bursts -system.physmem.perBankRdBursts::7 10209 # Per bank write bursts -system.physmem.perBankRdBursts::8 10543 # Per bank write bursts -system.physmem.perBankRdBursts::9 10609 # Per bank write bursts -system.physmem.perBankRdBursts::10 10499 # Per bank write bursts -system.physmem.perBankRdBursts::11 10227 # Per bank write bursts -system.physmem.perBankRdBursts::12 10274 # Per bank write bursts -system.physmem.perBankRdBursts::13 10565 # Per bank write bursts -system.physmem.perBankRdBursts::14 10463 # Per bank write bursts -system.physmem.perBankRdBursts::15 10564 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7274 # Per bank write bursts -system.physmem.perBankWrBursts::2 7296 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7187 # Per bank write bursts -system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7100 # Per bank write bursts -system.physmem.perBankWrBursts::8 7227 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7117 # Per bank write bursts -system.physmem.perBankWrBursts::11 7031 # Per bank write bursts -system.physmem.perBankWrBursts::12 6992 # Per bank write bursts -system.physmem.perBankWrBursts::13 7301 # Per bank write bursts -system.physmem.perBankWrBursts::14 7308 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10345 # Per bank write bursts +system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::2 10224 # Per bank write bursts +system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::4 10353 # Per bank write bursts +system.physmem.perBankRdBursts::5 10360 # Per bank write bursts +system.physmem.perBankRdBursts::6 9794 # Per bank write bursts +system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::8 10568 # Per bank write bursts +system.physmem.perBankRdBursts::9 10626 # Per bank write bursts +system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::11 10241 # Per bank write bursts +system.physmem.perBankRdBursts::12 10307 # Per bank write bursts +system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::14 10494 # Per bank write bursts +system.physmem.perBankRdBursts::15 10573 # Per bank write bursts +system.physmem.perBankWrBursts::0 7166 # Per bank write bursts +system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::2 7303 # Per bank write bursts +system.physmem.perBankWrBursts::3 7011 # Per bank write bursts +system.physmem.perBankWrBursts::4 7144 # Per bank write bursts +system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::6 6890 # Per bank write bursts +system.physmem.perBankWrBursts::7 7170 # Per bank write bursts +system.physmem.perBankWrBursts::8 7244 # Per bank write bursts +system.physmem.perBankWrBursts::9 7072 # Per bank write bursts +system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::11 7126 # Per bank write bursts +system.physmem.perBankWrBursts::12 7072 # Per bank write bursts +system.physmem.perBankWrBursts::13 7397 # Per bank write bursts +system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60000569500 # Total gap between requests +system.physmem.totGap 60093907500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165369 # Read request sizes (log2) +system.physmem.readPktSize::6 165736 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114468 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115250 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,126 +194,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.137094 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.166991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.705237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19617 35.84% 35.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11794 21.55% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5683 10.38% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3657 6.68% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2805 5.12% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2027 3.70% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1612 2.95% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1505 2.75% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6036 11.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54736 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.474162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.252876 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7042 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.246735 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.230854 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.753728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6287 89.25% 89.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 12 0.17% 89.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 574 8.15% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 138 1.96% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.26% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 7 0.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7044 # Writes before turning the bus around for reads -system.physmem.totQLat 1985984500 # Total ticks spent queuing -system.physmem.totMemAccLat 5086540750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12009.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads +system.physmem.totQLat 1892978500 # Total ticks spent queuing +system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30759.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.33 # Data bus utilization in percentage +system.physmem.busUtil 2.34 # Data bus utilization in percentage system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 143816 # Number of row buffer hits during reads -system.physmem.writeRowHits 81240 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.97 # Row buffer hit rate for writes -system.physmem.avgGap 214412.57 # Average gap between requests -system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 198964080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108561750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636386400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 369061920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12421358775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25100061000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42752848725 # Total energy per rank (pJ) -system.physmem_0.averagePower 712.626862 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41606215000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing +system.physmem.readRowHits 144145 # Number of row buffer hits during reads +system.physmem.writeRowHits 89685 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes +system.physmem.avgGap 213867.98 # Average gap between requests +system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) +system.physmem_0.averagePower 711.117850 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16383815000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214545240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117063375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652945800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 372211200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13100937570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24503939250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42880097235 # Total energy per rank (pJ) -system.physmem_1.averagePower 714.747907 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40611255500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) +system.physmem_1.averagePower 713.246634 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17379160000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14695118 # Number of BP lookups -system.cpu.branchPred.condPredicted 9500860 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 385258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10182600 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6367092 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696108 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.529138 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84621 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37568 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5776 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20578668 # DTB read hits -system.cpu.dtb.read_misses 95435 # DTB read misses +system.cpu.dtb.read_hits 20579333 # DTB read hits +system.cpu.dtb.read_misses 95423 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674103 # DTB read accesses -system.cpu.dtb.write_hits 14665915 # DTB write hits -system.cpu.dtb.write_misses 8842 # DTB write misses +system.cpu.dtb.read_accesses 20674756 # DTB read accesses +system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674757 # DTB write accesses -system.cpu.dtb.data_hits 35244583 # DTB hits -system.cpu.dtb.data_misses 104277 # DTB misses +system.cpu.dtb.write_accesses 14674875 # DTB write accesses +system.cpu.dtb.data_hits 35245368 # DTB hits +system.cpu.dtb.data_misses 104263 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35348860 # DTB accesses -system.cpu.itb.fetch_hits 25646396 # ITB hits -system.cpu.itb.fetch_misses 5177 # ITB misses +system.cpu.dtb.data_accesses 35349631 # DTB accesses +system.cpu.itb.fetch_hits 25649355 # ITB hits +system.cpu.itb.fetch_misses 5175 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25651573 # ITB accesses +system.cpu.itb.fetch_accesses 25654530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -327,16 +325,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120001186 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120187862 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1084586 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.356895 # CPI: cycles per instruction -system.cpu.ipc 0.736977 # IPC: instructions per cycle +system.cpu.cpi 1.359006 # CPI: cycles per instruction +system.cpu.ipc 0.735832 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -372,58 +370,58 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91986001 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28015185 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200807 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.707874 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647558 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204903 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092488 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 690770500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.707874 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy +system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200806 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3387 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70183301 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70183301 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314289 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314289 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333269 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333269 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647558 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647558 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647558 # number of overall hits -system.cpu.dcache.overall_hits::total 34647558 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280108 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280108 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341641 # number of overall misses -system.cpu.dcache.overall_misses::total 341641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24448426000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24448426000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20375822 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20375822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits +system.cpu.dcache.overall_hits::total 34648172 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses +system.cpu.dcache.overall_misses::total 341638 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989199 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses @@ -432,46 +430,46 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44505.379227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44505.379227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77505.378283 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77505.378283 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71561.744638 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168446 # number of writebacks -system.cpu.dcache.writebacks::total 168446 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15996.393676 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25493390 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25493390 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25493390 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25493390 # number of overall hits +system.cpu.icache.overall_hits::total 25493390 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155965 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155965 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155965 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155965 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155965 # number of overall misses +system.cpu.icache.overall_misses::total 155965 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2518921000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2518921000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2518921000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2518921000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2518921000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2518921000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25649355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25649355 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25649355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25649355 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006081 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006081 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006081 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006081 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16150.553009 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16150.553009 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16150.553009 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153927 # number of writebacks -system.cpu.icache.writebacks::total 153927 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155976 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155976 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155976 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155976 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30427.789253 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 406173 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 165503 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.454173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26336.336681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2098.353555 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1993.099017 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803721 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.060825 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928582 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1064 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979980 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 6033974 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 6033974 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153927 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153927 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 135276 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31728.322423 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 547427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168044 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.257641 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13928082000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 716.089195 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1994.899360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29017.333867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.021853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060879 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.885539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968272 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9499 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22051 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 5892756 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5892756 # 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miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043914 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775434 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.459274 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81323.628044 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81323.628044 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82221.784202 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82221.784202 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81496.408149 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81496.408149 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82221.784202 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158598 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165370 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6772 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158598 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165370 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9322858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9322858000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 470607500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 470607500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1951393000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1951393000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 470607500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11274251000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11744858500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 470607500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11274251000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11744858500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 115251 # number of writebacks +system.cpu.l2cache.writebacks::total 115251 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6849 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6849 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27980 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27980 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6849 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158888 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165737 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6849 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158888 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165737 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9336833500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9336833500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 494657000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 494657000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2000469500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2000469500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 494657000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11337303000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11831960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 494657000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11337303000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11831960000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911651 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911651 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043417 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451855 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451855 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774015 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.458242 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043417 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774015 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.458242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71230.473018 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71230.473018 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69493.133491 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69493.133491 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70409.272957 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70409.272957 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69493.133491 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71086.968310 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69493.133491 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71086.968310 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715613 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354734 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51284 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61336 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19833728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23894336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43728064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133391 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7325952 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 494270 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008147 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.089894 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135276 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 490243 99.19% 99.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4027 0.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 494270 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 680179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233962999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307359989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34486 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114468 # Transaction distribution -system.membus.trans_dist::CleanEvict 15010 # Transaction distribution -system.membus.trans_dist::ReadExReq 130883 # Transaction distribution -system.membus.trans_dist::ReadExResp 130883 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34486 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17909568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17909568 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34828 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution +system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.trans_dist::ReadExReq 130908 # Transaction distribution +system.membus.trans_dist::ReadExResp 130908 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294847 # Request fanout histogram +system.membus.snoop_fanout::samples 165736 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294847 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294847 # Request fanout histogram -system.membus.reqLayer0.occupancy 819183500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165736 # Request fanout histogram +system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 873079500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4fef80875..4f7e5b26f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022275 # Number of seconds simulated -sim_ticks 22275010500 # Number of ticks simulated -final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022294 # Number of seconds simulated +sim_ticks 22293541500 # Number of ticks simulated +final_tick 22293541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202670 # Simulator instruction rate (inst/s) -host_op_rate 202670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56720302 # Simulator tick rate (ticks/s) -host_mem_usage 259380 # Number of bytes of host memory used -host_seconds 392.72 # Real time elapsed on the host +host_inst_rate 223643 # Simulator instruction rate (inst/s) +host_op_rate 223643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62642230 # Simulator tick rate (ticks/s) +host_mem_usage 265292 # Number of bytes of host memory used +host_seconds 355.89 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory -system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7322816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7322816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114419 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114419 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18405558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455811951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 474217509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 328745793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18405558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455811951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802963303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165050 # Number of read requests accepted -system.physmem.writeReqs 114419 # Number of write requests accepted -system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114419 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7320960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7322816 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 413888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10171008 # Number of bytes read from this memory +system.physmem.bytes_read::total 10584896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158922 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18565377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456231147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 474796523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 330714615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18565377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456231147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 805511139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165389 # Number of read requests accepted +system.physmem.writeReqs 115200 # Number of write requests accepted +system.physmem.readBursts 165389 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115200 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10584320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7371392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10584896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10290 # Per bank write bursts -system.physmem.perBankRdBursts::1 10331 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10021 # Per bank write bursts -system.physmem.perBankRdBursts::4 10343 # Per bank write bursts -system.physmem.perBankRdBursts::5 10313 # Per bank write bursts -system.physmem.perBankRdBursts::6 9783 # Per bank write bursts -system.physmem.perBankRdBursts::7 10190 # Per bank write bursts -system.physmem.perBankRdBursts::8 10528 # Per bank write bursts -system.physmem.perBankRdBursts::9 10599 # Per bank write bursts -system.physmem.perBankRdBursts::10 10456 # Per bank write bursts -system.physmem.perBankRdBursts::11 10208 # Per bank write bursts -system.physmem.perBankRdBursts::12 10247 # Per bank write bursts -system.physmem.perBankRdBursts::13 10535 # Per bank write bursts -system.physmem.perBankRdBursts::14 10446 # Per bank write bursts -system.physmem.perBankRdBursts::15 10548 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7268 # Per bank write bursts -system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts -system.physmem.perBankWrBursts::6 6836 # Per bank write bursts -system.physmem.perBankWrBursts::7 7101 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7101 # Per bank write bursts -system.physmem.perBankWrBursts::11 7022 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7296 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10310 # Per bank write bursts +system.physmem.perBankRdBursts::1 10350 # Per bank write bursts +system.physmem.perBankRdBursts::2 10221 # Per bank write bursts +system.physmem.perBankRdBursts::3 10037 # Per bank write bursts +system.physmem.perBankRdBursts::4 10349 # Per bank write bursts +system.physmem.perBankRdBursts::5 10325 # Per bank write bursts +system.physmem.perBankRdBursts::6 9802 # Per bank write bursts +system.physmem.perBankRdBursts::7 10210 # Per bank write bursts +system.physmem.perBankRdBursts::8 10556 # Per bank write bursts +system.physmem.perBankRdBursts::9 10619 # Per bank write bursts +system.physmem.perBankRdBursts::10 10516 # Per bank write bursts +system.physmem.perBankRdBursts::11 10224 # Per bank write bursts +system.physmem.perBankRdBursts::12 10277 # Per bank write bursts +system.physmem.perBankRdBursts::13 10556 # Per bank write bursts +system.physmem.perBankRdBursts::14 10475 # Per bank write bursts +system.physmem.perBankRdBursts::15 10553 # Per bank write bursts +system.physmem.perBankWrBursts::0 7167 # Per bank write bursts +system.physmem.perBankWrBursts::1 7278 # Per bank write bursts +system.physmem.perBankWrBursts::2 7300 # Per bank write bursts +system.physmem.perBankWrBursts::3 7008 # Per bank write bursts +system.physmem.perBankWrBursts::4 7143 # Per bank write bursts +system.physmem.perBankWrBursts::5 7301 # Per bank write bursts +system.physmem.perBankWrBursts::6 6892 # Per bank write bursts +system.physmem.perBankWrBursts::7 7161 # Per bank write bursts +system.physmem.perBankWrBursts::8 7241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7068 # Per bank write bursts +system.physmem.perBankWrBursts::10 7202 # Per bank write bursts +system.physmem.perBankWrBursts::11 7125 # Per bank write bursts +system.physmem.perBankWrBursts::12 7069 # Per bank write bursts +system.physmem.perBankWrBursts::13 7390 # Per bank write bursts +system.physmem.perBankWrBursts::14 7350 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22274979500 # Total gap between requests +system.physmem.totGap 22293510500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165050 # Read request sizes (log2) +system.physmem.readPktSize::6 165389 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114419 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115200 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,33 +145,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,127 +194,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.896604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.837447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.790414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18483 35.34% 35.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10568 20.20% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5879 11.24% 66.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2936 5.61% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2943 5.63% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1490 2.85% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2026 3.87% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 952 1.82% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7027 13.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52304 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.609728 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.236069 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6988 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.364807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.334911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.053834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6086 87.07% 87.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.50% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 6.51% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 219 3.13% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 100 1.43% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 53 0.76% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 22 0.31% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.10% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads -system.physmem.totQLat 5740232250 # Total ticks spent queuing -system.physmem.totMemAccLat 8834807250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34780.01 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 44806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 400.727760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.628821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 367.162466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13215 29.49% 29.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8315 18.56% 48.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5340 11.92% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2750 6.14% 66.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2605 5.81% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 3.56% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1654 3.69% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1106 2.47% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8228 18.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 44806 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.298957 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.933264 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 317.077516 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7097 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7098 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.226824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.209944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.780993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6477 91.25% 91.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 22 0.31% 91.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 336 4.73% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 168 2.37% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 66 0.93% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.38% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7098 # Writes before turning the bus around for reads +system.physmem.totQLat 5599085250 # Total ticks spent queuing +system.physmem.totMemAccLat 8699960250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33855.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53530.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 474.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 328.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 474.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 328.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52605.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 474.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 330.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 474.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 330.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes +system.physmem.busUtil 6.29 # Data bus utilization in percentage +system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.58 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing -system.physmem.readRowHits 145488 # Number of row buffer hits during reads -system.physmem.writeRowHits 81629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.34 # Row buffer hit rate for writes -system.physmem.avgGap 79704.65 # Average gap between requests -system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190428840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103904625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 635177400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368951760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6564184695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7603330500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16920459420 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.821975 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12566232250 # Time in different power states -system.physmem_0.memoryStateTime::REF 743600000 # Time in different power states +system.physmem.avgWrQLen 24.72 # Average write queue length when enqueuing +system.physmem.readRowHits 145830 # Number of row buffer hits during reads +system.physmem.writeRowHits 89913 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes +system.physmem.avgGap 79452.55 # Average gap between requests +system.physmem.pageHitRate 84.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 163424520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 89170125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636441000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370882800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6110627715 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8015176500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16841729940 # Total energy per rank (pJ) +system.physmem_0.averagePower 755.495604 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 13256940500 # Time in different power states +system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8959159250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8290987000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204618960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111647250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371861280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6822625545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7376602500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16993402335 # Total energy per rank (pJ) -system.physmem_1.averagePower 763.098971 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12188749750 # Time in different power states -system.physmem_1.memoryStateTime::REF 743600000 # Time in different power states +system.physmem_1.actEnergy 175218120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 95605125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 653343600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375366960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6480752940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7690505250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16926799275 # Total energy per rank (pJ) +system.physmem_1.averagePower 759.311692 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12714890500 # Time in different power states +system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8833037000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16474744 # Number of BP lookups -system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8918177 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7235165 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16464676 # Number of BP lookups +system.cpu.branchPred.condPredicted 10658312 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 322373 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8884191 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7232535 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.128296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1973322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3328 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39379 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31470 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7909 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2657 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 81.409044 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1975403 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3321 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39323 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31540 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7783 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2655 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22508484 # DTB read hits -system.cpu.dtb.read_misses 226837 # DTB read misses +system.cpu.dtb.read_hits 22505585 # DTB read hits +system.cpu.dtb.read_misses 226699 # DTB read misses system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22735321 # DTB read accesses -system.cpu.dtb.write_hits 15806842 # DTB write hits -system.cpu.dtb.write_misses 44564 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15851406 # DTB write accesses -system.cpu.dtb.data_hits 38315326 # DTB hits -system.cpu.dtb.data_misses 271401 # DTB misses -system.cpu.dtb.data_acv 20 # DTB access violations -system.cpu.dtb.data_accesses 38586727 # DTB accesses -system.cpu.itb.fetch_hits 13727245 # ITB hits -system.cpu.itb.fetch_misses 29559 # ITB misses +system.cpu.dtb.read_accesses 22732284 # DTB read accesses +system.cpu.dtb.write_hits 15808846 # DTB write hits +system.cpu.dtb.write_misses 44546 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15853392 # DTB write accesses +system.cpu.dtb.data_hits 38314431 # DTB hits +system.cpu.dtb.data_misses 271245 # DTB misses +system.cpu.dtb.data_acv 22 # DTB access violations +system.cpu.dtb.data_accesses 38585676 # DTB accesses +system.cpu.itb.fetch_hits 13724143 # ITB hits +system.cpu.itb.fetch_misses 29345 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13756804 # ITB accesses +system.cpu.itb.fetch_accesses 13753488 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,142 +326,142 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44550025 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44587088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15536362 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105039044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16474744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9239957 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27563903 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 886514 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 244 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 331564 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 78 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13727245 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187963 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15537600 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105003279 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16464676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9239478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27573681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 883330 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 330450 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13724143 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187041 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.393772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.128235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.392505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.127693 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24375049 55.55% 55.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1515026 3.45% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1375639 3.13% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1503768 3.43% 65.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4189647 9.55% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1825739 4.16% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 668569 1.52% 80.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050805 2.39% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7375888 16.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24387762 55.57% 55.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1515251 3.45% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1377134 3.14% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1500310 3.42% 65.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4190997 9.55% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1825571 4.16% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669926 1.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050385 2.39% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7371092 16.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369803 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.357777 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14899233 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9760394 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18283223 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 591754 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 345526 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3700749 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99293 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103056970 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314917 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 345526 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15243567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4452634 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97322 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18515033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5226048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102057831 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7235 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94720 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 348136 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4717245 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61355857 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123078605 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122759511 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319093 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369270 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.355015 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14897050 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9776190 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18280655 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 589828 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 344705 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3701787 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98635 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103032848 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312916 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 344705 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15240775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4552016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97125 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18511621 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5142186 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102032260 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5895 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 92509 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 354670 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4626637 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61342957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123044735 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122725402 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8808976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5695 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5747 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2360993 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23135657 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16359365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1252776 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502701 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90727911 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5569 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88607473 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70141 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11141723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4452155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 986 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43880130 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.019307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245631 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8796076 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5684 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5736 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2358572 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23134576 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16358313 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246652 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 504576 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88603709 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68043 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11133526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4439018 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 973 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43888428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.245634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17424086 39.71% 39.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5721163 13.04% 52.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5107482 11.64% 64.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4378378 9.98% 74.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4320360 9.85% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2636536 6.01% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1944467 4.43% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1375974 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 971684 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17434377 39.72% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5720394 13.03% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5103914 11.63% 64.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4383916 9.99% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4317842 9.84% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2637316 6.01% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1940633 4.42% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1378295 3.14% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 971741 2.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43880130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43888428 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243434 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1167545 46.27% 55.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112329 44.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 241284 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1166228 46.24% 55.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1114848 44.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49382948 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43980 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49379489 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44005 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121151 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121171 0.14% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120663 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120707 0.14% 56.05% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39093 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39092 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -485,82 +483,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22902831 25.85% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15996653 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22899221 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15999870 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88607473 # Type of FU issued -system.cpu.iq.rate 1.988943 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223077288 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101475255 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86832445 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420100 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299852 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90825011 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305770 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1671661 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88603709 # Type of FU issued +system.cpu.iq.rate 1.987206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2522360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223074890 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101458980 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86835527 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299878 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90820238 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1672227 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2859019 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5476 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1745988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2857938 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5878 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20874 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1744936 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3024 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205293 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3021 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 200758 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 345526 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1271875 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2754338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100226384 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125320 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23135657 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16359365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5569 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3722 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2752972 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 115768 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 151556 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 267324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87911556 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22736014 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 344705 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1315985 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2729229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100214269 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 118431 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23134576 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16358313 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5556 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3898 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2727794 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20874 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 113179 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 152389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 265568 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87909421 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22732927 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 694288 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9492904 # number of nop insts executed -system.cpu.iew.exec_refs 38587764 # number of memory reference insts executed -system.cpu.iew.exec_branches 15119893 # Number of branches executed -system.cpu.iew.exec_stores 15851750 # Number of stores executed -system.cpu.iew.exec_rate 1.973322 # Inst execution rate -system.cpu.iew.wb_sent 87534383 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87132297 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33840523 # num instructions producing a value -system.cpu.iew.wb_consumers 44256350 # num instructions consuming a value -system.cpu.iew.wb_rate 1.955830 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764648 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8655398 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9488986 # number of nop insts executed +system.cpu.iew.exec_refs 38586655 # number of memory reference insts executed +system.cpu.iew.exec_branches 15119960 # Number of branches executed +system.cpu.iew.exec_stores 15853728 # Number of stores executed +system.cpu.iew.exec_rate 1.971634 # Inst execution rate +system.cpu.iew.wb_sent 87537444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87135405 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33842966 # num instructions producing a value +system.cpu.iew.wb_consumers 44247648 # num instructions consuming a value +system.cpu.iew.wb_rate 1.954274 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764853 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8653815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 226701 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42610108 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.073233 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.886041 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 225413 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42617548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.072871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885939 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21149437 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6275459 14.73% 64.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2900348 6.81% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1740796 4.09% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1682035 3.95% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1127009 2.64% 81.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1202859 2.82% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795530 1.87% 86.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5736635 13.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21149374 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6281932 14.74% 64.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2908445 6.82% 71.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1738602 4.08% 75.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1681485 3.95% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1121192 2.63% 81.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1200701 2.82% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 796598 1.87% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5739219 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42610108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42617548 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -606,465 +604,471 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5736635 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132552201 # The number of ROB reads -system.cpu.rob.rob_writes 195265380 # The number of ROB writes -system.cpu.timesIdled 45343 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 669895 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5739219 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132555474 # The number of ROB reads +system.cpu.rob.rob_writes 195263120 # The number of ROB writes +system.cpu.timesIdled 45271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 698660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559732 # CPI: Total CPI of All Threads -system.cpu.ipc 1.786570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.786570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116366061 # number of integer regfile reads -system.cpu.int_regfile_writes 57668563 # number of integer regfile writes -system.cpu.fp_regfile_reads 255567 # number of floating regfile reads -system.cpu.fp_regfile_writes 240367 # number of floating regfile writes -system.cpu.misc_regfile_reads 38271 # number of misc regfile reads +system.cpu.cpi 0.560197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.560197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.785085 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.785085 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116363135 # number of integer regfile reads +system.cpu.int_regfile_writes 57669565 # number of integer regfile writes +system.cpu.fp_regfile_reads 255561 # number of floating regfile reads +system.cpu.fp_regfile_writes 240404 # number of floating regfile writes +system.cpu.misc_regfile_reads 38263 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201418 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205514 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.365026 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.642288 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993809 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 201400 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.443451 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33984025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205496 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.375603 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 232048500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.443451 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1341 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561123 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33984765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33984765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33984765 # number of overall hits -system.cpu.dcache.overall_hits::total 33984765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269234 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052254 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052254 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321488 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321488 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321488 # number of overall misses -system.cpu.dcache.overall_misses::total 1321488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106412829377 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106412829377 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20692876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20692876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70817108 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70817108 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20422994 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20422994 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13560978 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13560978 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33983972 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33983972 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33983972 # number of overall hits +system.cpu.dcache.overall_hits::total 33983972 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269382 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269382 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052399 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052399 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321781 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321781 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321781 # number of overall misses +system.cpu.dcache.overall_misses::total 1321781 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106464627659 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106464627659 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20692376 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20692376 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35306253 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35306253 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35306253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35306253 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037429 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037429 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037429 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6873080 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 89218 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35305753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35305753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35305753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35305753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037438 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037438 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037438 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037438 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6874865 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 86609 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.036921 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168806 # number of writebacks -system.cpu.dcache.writebacks::total 168806 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207108 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908866 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908866 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115974 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62126 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62126 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143388 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143388 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205514 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205514 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.378182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 139.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168502 # number of writebacks +system.cpu.dcache.writebacks::total 168502 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207279 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207279 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 909006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 909006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1116285 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1116285 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62103 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90292 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92340 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.524063 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18757985500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.963164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936017 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936017 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 90436 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.490065 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13619166 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92484 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.259699 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18779712500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.490065 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935786 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935786 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 384 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1460 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 389 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13622372 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13622372 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1921920999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13727244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13727244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13727244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13727244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13727244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13727244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007640 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007640 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007640 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007640 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007640 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007640 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18326.350208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18326.350208 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18326.350208 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18326.350208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18326.350208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18326.350208 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27540768 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27540768 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 13619166 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13619166 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13619166 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13619166 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13619166 # number of overall hits +system.cpu.icache.overall_hits::total 13619166 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 104976 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 104976 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 104976 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 104976 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 104976 # number of overall misses +system.cpu.icache.overall_misses::total 104976 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1956506499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1956506499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1956506499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1956506499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1956506499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1956506499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13724142 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13724142 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13724142 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13724142 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13724142 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13724142 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007649 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007649 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007649 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007649 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007649 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007649 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18637.655264 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18637.655264 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18637.655264 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18637.655264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18637.655264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18637.655264 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1136 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 75.733333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 90292 # number of writebacks -system.cpu.icache.writebacks::total 90292 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12531 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12531 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12531 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12531 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12531 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12531 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92341 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 92341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 92341 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 92341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 92341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 92341 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1570228500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1570228500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1570228500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1570228500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1570228500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1570228500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006727 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006727 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006727 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17004.672897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17004.672897 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133082 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30595.837110 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 280630 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 165175 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.698986 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26800.034004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1869.508141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1926.294965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.817872 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.058786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.933711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32093 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28315 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 361 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979401 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5025086 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5025086 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168806 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168806 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62123 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 62123 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 92341 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205514 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 297855 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 92341 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205514 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 297855 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912052 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912052 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069384 # 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mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554132 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589565 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291710 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555035 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589817 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291836 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4239 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62123 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 274973 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887419 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11688448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35644928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133082 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7322816 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 430937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009387 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096428 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 154585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52571 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275405 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887797 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11706880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23935872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35642752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134874 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7372864 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 432855 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009793 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 426892 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4045 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428616 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4239 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 430937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553880500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432855 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553846500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138521976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 138734483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308248491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34270 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution -system.membus.trans_dist::CleanEvict 14728 # Transaction distribution -system.membus.trans_dist::ReadExReq 130780 # Transaction distribution -system.membus.trans_dist::ReadExResp 130780 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34270 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17886016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17886016 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 130746 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34578 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115200 # Transaction distribution +system.membus.trans_dist::CleanEvict 15546 # Transaction distribution +system.membus.trans_dist::ReadExReq 130811 # Transaction distribution +system.membus.trans_dist::ReadExResp 130811 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34578 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17957696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294197 # Request fanout histogram +system.membus.snoop_fanout::samples 165389 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165389 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294197 # Request fanout histogram -system.membus.reqLayer0.occupancy 776999500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165389 # Request fanout histogram +system.membus.reqLayer0.occupancy 780841500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 852713250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 854544750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- |