diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/se/50.vortex/ref/alpha/tru64 | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64')
6 files changed, 1395 insertions, 1356 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini index 4117f093b..46094eb94 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout index dcc24233a..a86af0918 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4306 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28063 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 60000593000 because target called exit() +Exiting @ tick 61709224000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 58628a22b..4a990b700 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060094 # Number of seconds simulated -sim_ticks 60093931000 # Number of ticks simulated -final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061709 # Number of seconds simulated +sim_ticks 61709224000 # Number of ticks simulated +final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 276952 # Simulator instruction rate (inst/s) -host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188189933 # Simulator tick rate (ticks/s) -host_mem_usage 264524 # Number of bytes of host memory used -host_seconds 319.33 # Real time elapsed on the host +host_inst_rate 242211 # Simulator instruction rate (inst/s) +host_op_rate 242211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 169006859 # Simulator tick rate (ticks/s) +host_mem_usage 262168 # Number of bytes of host memory used +host_seconds 365.13 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165736 # Number of read requests accepted -system.physmem.writeReqs 115250 # Number of write requests accepted -system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165740 # Number of read requests accepted +system.physmem.writeReqs 115251 # Number of write requests accepted +system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::1 10387 # Per bank write bursts system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::3 10068 # Per bank write bursts system.physmem.perBankRdBursts::4 10353 # Per bank write bursts system.physmem.perBankRdBursts::5 10360 # Per bank write bursts system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::7 10230 # Per bank write bursts system.physmem.perBankRdBursts::8 10568 # Per bank write bursts system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::10 10568 # Per bank write bursts system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10307 # Per bank write bursts -system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::12 10306 # Per bank write bursts +system.physmem.perBankRdBursts::13 10592 # Per bank write bursts system.physmem.perBankRdBursts::14 10494 # Per bank write bursts system.physmem.perBankRdBursts::15 10573 # Per bank write bursts system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::1 7281 # Per bank write bursts system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7011 # Per bank write bursts -system.physmem.perBankWrBursts::4 7144 # Per bank write bursts -system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::3 7012 # Per bank write bursts +system.physmem.perBankWrBursts::4 7145 # Per bank write bursts +system.physmem.perBankWrBursts::5 7305 # Per bank write bursts system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7170 # Per bank write bursts -system.physmem.perBankWrBursts::8 7244 # Per bank write bursts -system.physmem.perBankWrBursts::9 7072 # Per bank write bursts -system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::7 7164 # Per bank write bursts +system.physmem.perBankWrBursts::8 7246 # Per bank write bursts +system.physmem.perBankWrBursts::9 7071 # Per bank write bursts +system.physmem.perBankWrBursts::10 7213 # Per bank write bursts system.physmem.perBankWrBursts::11 7126 # Per bank write bursts system.physmem.perBankWrBursts::12 7072 # Per bank write bursts system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::14 7351 # Per bank write bursts system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60093907500 # Total gap between requests +system.physmem.totGap 61709200500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165736 # Read request sizes (log2) +system.physmem.readPktSize::6 165740 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115250 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115251 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,124 +194,134 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads -system.physmem.totQLat 1892978500 # Total ticks spent queuing -system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads +system.physmem.totQLat 3617300750 # Total ticks spent queuing +system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.34 # Data bus utilization in percentage -system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing -system.physmem.readRowHits 144145 # Number of row buffer hits during reads -system.physmem.writeRowHits 89685 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes -system.physmem.avgGap 213867.98 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) -system.physmem_0.averagePower 711.117850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) -system.physmem_1.averagePower 713.246634 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696108 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits +system.physmem.busUtil 2.28 # Data bus utilization in percentage +system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing +system.physmem.readRowHits 144262 # Number of row buffer hits during reads +system.physmem.writeRowHits 89468 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes +system.physmem.avgGap 219612.73 # Average gap between requests +system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) +system.physmem_0.averagePower 393.299410 # Core power per rank (mW) +system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states +system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) +system.physmem_1.averagePower 400.858918 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696527 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579333 # DTB read hits -system.cpu.dtb.read_misses 95423 # DTB read misses +system.cpu.dtb.read_hits 20579387 # DTB read hits +system.cpu.dtb.read_misses 95377 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674756 # DTB read accesses -system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.read_accesses 20674764 # DTB read accesses +system.cpu.dtb.write_hits 14666029 # DTB write hits system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674875 # DTB write accesses -system.cpu.dtb.data_hits 35245368 # DTB hits -system.cpu.dtb.data_misses 104263 # DTB misses +system.cpu.dtb.write_accesses 14674869 # DTB write accesses +system.cpu.dtb.data_hits 35245416 # DTB hits +system.cpu.dtb.data_misses 104217 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349631 # DTB accesses -system.cpu.itb.fetch_hits 25649355 # ITB hits -system.cpu.itb.fetch_misses 5175 # ITB misses +system.cpu.dtb.data_accesses 35349633 # DTB accesses +system.cpu.itb.fetch_hits 25650137 # ITB hits +system.cpu.itb.fetch_misses 5179 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25654530 # ITB accesses +system.cpu.itb.fetch_accesses 25655316 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,16 +335,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120187862 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 123418448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359006 # CPI: cycles per instruction -system.cpu.ipc 0.735832 # IPC: instructions per cycle +system.cpu.cpi 1.395535 # CPI: cycles per instruction +system.cpu.ipc 0.716571 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -370,106 +380,106 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200806 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy +system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked +system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200809 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits -system.cpu.dcache.overall_hits::total 34648172 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses -system.cpu.dcache.overall_misses::total 341638 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits +system.cpu.dcache.overall_hits::total 34647996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses +system.cpu.dcache.overall_misses::total 341611 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks -system.cpu.dcache.writebacks::total 168116 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136736 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61335 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61335 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168117 # number of writebacks +system.cpu.dcache.writebacks::total 168117 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136509 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136509 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 136706 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 136706 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 136706 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 136706 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61338 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61338 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204902 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204902 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204902 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204902 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2722762000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2722762000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994246500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994246500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13717008500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13717008500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13717008500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13717008500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3088657500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -478,338 +488,338 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153916 # number of replacements -system.cpu.icache.tags.tagsinuse 1931.382130 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25493390 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155964 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.456887 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42683279500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1931.382130 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943058 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50354.714859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50354.714859 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84853.890518 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84853.890518 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 153962 # number of replacements +system.cpu.icache.tags.tagsinuse 1929.475732 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25494126 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 156010 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.413409 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 43906590500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1929.475732 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.942127 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.942127 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1033 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 801 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25493390 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25493390 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25493390 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25493390 # number of overall hits -system.cpu.icache.overall_hits::total 25493390 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155965 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155965 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155965 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155965 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155965 # number of overall misses -system.cpu.icache.overall_misses::total 155965 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2518921000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2518921000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2518921000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2518921000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2518921000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2518921000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25649355 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25649355 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25649355 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25649355 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25649355 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25649355 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006081 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006081 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006081 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006081 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006081 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006081 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16150.553009 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16150.553009 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16150.553009 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16150.553009 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51456284 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51456284 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25494126 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25494126 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25494126 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25494126 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25494126 # number of overall hits +system.cpu.icache.overall_hits::total 25494126 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 156011 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 156011 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 156011 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 156011 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 156011 # number of overall misses +system.cpu.icache.overall_misses::total 156011 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2690499000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2690499000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2690499000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2690499000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2690499000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2690499000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25650137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25650137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25650137 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25650137 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25650137 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25650137 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17245.572428 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17245.572428 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17245.572428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17245.572428 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153916 # number of writebacks -system.cpu.icache.writebacks::total 153916 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155965 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155965 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155965 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2362957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2362957000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2362957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2362957000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2362957000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2362957000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15150.559420 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15150.559420 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 135276 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31728.322423 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 547427 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168044 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.257641 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13928082000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 716.089195 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1994.899360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29017.333867 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021853 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060879 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.885539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968272 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 153962 # number of writebacks +system.cpu.icache.writebacks::total 153962 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 156011 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 156011 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 156011 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 156011 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 156011 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 156011 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2534489000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2534489000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2534489000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2534489000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2534489000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2534489000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 135280 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31691.220276 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 547521 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168048 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.258123 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 14447297000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 710.430921 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1986.776331 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28994.013023 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.021681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060632 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.884827 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.967139 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9499 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22051 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 8856 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22759 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5892756 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5892756 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168116 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168116 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153916 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153916 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 5893544 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5893544 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 168117 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168117 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 153962 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 153962 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149116 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149116 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149161 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 149161 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149116 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 149161 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195130 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149116 # number of overall hits +system.cpu.l2cache.demand_hits::total 195175 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 149161 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits -system.cpu.l2cache.overall_hits::total 195130 # number of overall hits +system.cpu.l2cache.overall_hits::total 195175 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6849 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6849 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27980 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27980 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6849 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158888 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165737 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6849 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158888 # number of overall misses -system.cpu.l2cache.overall_misses::total 165737 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10645913500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10645913500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 563137000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 563137000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2280269500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2280269500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 563137000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12926183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13489320000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 563137000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12926183000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13489320000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168116 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168116 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 153916 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 153916 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6850 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6850 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27983 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 27983 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6850 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158891 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165741 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6850 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158891 # number of overall misses +system.cpu.l2cache.overall_misses::total 165741 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11833894500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11833894500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 734127500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 734127500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2646160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2646160500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 734127500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14480055000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15214182500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 734127500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14480055000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15214182500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168117 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168117 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 153962 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 153962 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 155965 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 155965 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61335 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61335 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 155965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204902 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360867 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 155965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204902 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360867 # number of overall (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 156011 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 156011 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61338 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 61338 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 156011 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 360916 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 156011 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 360916 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043914 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043914 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456183 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456183 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043914 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775434 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.459274 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043914 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775434 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.459274 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81323.628044 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81323.628044 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82221.784202 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82221.784202 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81496.408149 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81496.408149 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82221.784202 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81354.054428 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81389.912934 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82221.784202 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81354.054428 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81389.912934 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043907 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043907 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456210 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456210 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043907 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775437 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.459223 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043907 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775437 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.459223 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90398.558530 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115251 # number of writebacks -system.cpu.l2cache.writebacks::total 115251 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 115252 # number of writebacks +system.cpu.l2cache.writebacks::total 115252 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6849 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6849 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27980 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27980 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6849 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158888 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165737 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6849 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158888 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165737 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9336833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9336833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 494657000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 494657000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2000469500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2000469500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 494657000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11337303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11831960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 494657000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11337303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11831960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135276 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135280 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34828 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution -system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34832 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution +system.membus.trans_dist::CleanEvict 15886 # Transaction distribution system.membus.trans_dist::ReadExReq 130908 # Transaction distribution system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165736 # Request fanout histogram +system.membus.snoop_fanout::samples 165740 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165736 # Request fanout histogram -system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +system.membus.snoop_fanout::total 165740 # Request fanout histogram +system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index d19d770e5..42d282c4a 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index e4880ad37..03964c60a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4308 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28054 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 22275010500 because target called exit() +Exiting @ tick 22819771500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4f7e5b26f..6ed69f426 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022294 # Number of seconds simulated -sim_ticks 22293541500 # Number of ticks simulated -final_tick 22293541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022820 # Number of seconds simulated +sim_ticks 22819771500 # Number of ticks simulated +final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 223643 # Simulator instruction rate (inst/s) -host_op_rate 223643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62642230 # Simulator tick rate (ticks/s) -host_mem_usage 265292 # Number of bytes of host memory used -host_seconds 355.89 # Real time elapsed on the host +host_inst_rate 186519 # Simulator instruction rate (inst/s) +host_op_rate 186519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53476835 # Simulator tick rate (ticks/s) +host_mem_usage 263708 # Number of bytes of host memory used +host_seconds 426.72 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 413888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10171008 # Number of bytes read from this memory -system.physmem.bytes_read::total 10584896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 413888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 413888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 7372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158922 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115200 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18565377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456231147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 474796523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18565377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18565377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 330714615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 330714615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 330714615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18565377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456231147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805511139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165389 # Number of read requests accepted -system.physmem.writeReqs 115200 # Number of write requests accepted -system.physmem.readBursts 165389 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115200 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10584320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7371392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10584896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7372800 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 414016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10170944 # Number of bytes read from this memory +system.physmem.bytes_read::total 10584960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 414016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 414016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 7372608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158921 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18142864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 445707530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 463850394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18142864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18142864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323079835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323079835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323079835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18142864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 445707530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 786930228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165390 # Number of read requests accepted +system.physmem.writeReqs 115197 # Number of write requests accepted +system.physmem.readBursts 165390 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115197 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10584512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7370752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10584960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7372608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10310 # Per bank write bursts -system.physmem.perBankRdBursts::1 10350 # Per bank write bursts +system.physmem.perBankRdBursts::1 10353 # Per bank write bursts system.physmem.perBankRdBursts::2 10221 # Per bank write bursts -system.physmem.perBankRdBursts::3 10037 # Per bank write bursts +system.physmem.perBankRdBursts::3 10036 # Per bank write bursts system.physmem.perBankRdBursts::4 10349 # Per bank write bursts -system.physmem.perBankRdBursts::5 10325 # Per bank write bursts +system.physmem.perBankRdBursts::5 10326 # Per bank write bursts system.physmem.perBankRdBursts::6 9802 # Per bank write bursts -system.physmem.perBankRdBursts::7 10210 # Per bank write bursts -system.physmem.perBankRdBursts::8 10556 # Per bank write bursts -system.physmem.perBankRdBursts::9 10619 # Per bank write bursts +system.physmem.perBankRdBursts::7 10209 # Per bank write bursts +system.physmem.perBankRdBursts::8 10557 # Per bank write bursts +system.physmem.perBankRdBursts::9 10617 # Per bank write bursts system.physmem.perBankRdBursts::10 10516 # Per bank write bursts -system.physmem.perBankRdBursts::11 10224 # Per bank write bursts -system.physmem.perBankRdBursts::12 10277 # Per bank write bursts -system.physmem.perBankRdBursts::13 10556 # Per bank write bursts +system.physmem.perBankRdBursts::11 10223 # Per bank write bursts +system.physmem.perBankRdBursts::12 10279 # Per bank write bursts +system.physmem.perBankRdBursts::13 10557 # Per bank write bursts system.physmem.perBankRdBursts::14 10475 # Per bank write bursts system.physmem.perBankRdBursts::15 10553 # Per bank write bursts system.physmem.perBankWrBursts::0 7167 # Per bank write bursts -system.physmem.perBankWrBursts::1 7278 # Per bank write bursts +system.physmem.perBankWrBursts::1 7277 # Per bank write bursts system.physmem.perBankWrBursts::2 7300 # Per bank write bursts system.physmem.perBankWrBursts::3 7008 # Per bank write bursts -system.physmem.perBankWrBursts::4 7143 # Per bank write bursts -system.physmem.perBankWrBursts::5 7301 # Per bank write bursts +system.physmem.perBankWrBursts::4 7142 # Per bank write bursts +system.physmem.perBankWrBursts::5 7300 # Per bank write bursts system.physmem.perBankWrBursts::6 6892 # Per bank write bursts -system.physmem.perBankWrBursts::7 7161 # Per bank write bursts -system.physmem.perBankWrBursts::8 7241 # Per bank write bursts -system.physmem.perBankWrBursts::9 7068 # Per bank write bursts +system.physmem.perBankWrBursts::7 7158 # Per bank write bursts +system.physmem.perBankWrBursts::8 7240 # Per bank write bursts +system.physmem.perBankWrBursts::9 7069 # Per bank write bursts system.physmem.perBankWrBursts::10 7202 # Per bank write bursts -system.physmem.perBankWrBursts::11 7125 # Per bank write bursts +system.physmem.perBankWrBursts::11 7121 # Per bank write bursts system.physmem.perBankWrBursts::12 7069 # Per bank write bursts system.physmem.perBankWrBursts::13 7390 # Per bank write bursts system.physmem.perBankWrBursts::14 7350 # Per bank write bursts system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22293510500 # Total gap between requests +system.physmem.totGap 22819740500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165389 # Read request sizes (log2) +system.physmem.readPktSize::6 165390 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115200 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115197 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,125 +194,136 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 44806 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 400.727760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.628821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.162466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13215 29.49% 29.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8315 18.56% 48.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5340 11.92% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2750 6.14% 66.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2605 5.81% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1593 3.56% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1654 3.69% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1106 2.47% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8228 18.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 44806 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.298957 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.933264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 317.077516 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7097 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 44648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 402.130084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 240.586732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 367.720381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13091 29.32% 29.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8315 18.62% 47.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5360 12.01% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2692 6.03% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2549 5.71% 71.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1575 3.53% 75.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1705 3.82% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1125 2.52% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8236 18.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 44648 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.304961 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.955367 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 317.126574 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7095 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7098 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.226824 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.209944 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.780993 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6477 91.25% 91.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 22 0.31% 91.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 336 4.73% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 168 2.37% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 66 0.93% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 27 0.38% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7098 # Writes before turning the bus around for reads -system.physmem.totQLat 5599085250 # Total ticks spent queuing -system.physmem.totMemAccLat 8699960250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33855.88 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7096 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.229989 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.211978 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.816035 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6480 91.32% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.25% 91.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 334 4.71% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 161 2.27% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 74 1.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 24 0.34% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7096 # Writes before turning the bus around for reads +system.physmem.totQLat 7131716500 # Total ticks spent queuing +system.physmem.totMemAccLat 10232647750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43122.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52605.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 474.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 330.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 474.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 330.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 61872.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 463.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 463.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.58 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.72 # Average write queue length when enqueuing -system.physmem.readRowHits 145830 # Number of row buffer hits during reads -system.physmem.writeRowHits 89913 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes -system.physmem.avgGap 79452.55 # Average gap between requests -system.physmem.pageHitRate 84.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 163424520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 89170125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636441000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 370882800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6110627715 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8015176500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16841729940 # Total energy per rank (pJ) -system.physmem_0.averagePower 755.495604 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 13256940500 # Time in different power states -system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8290987000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 175218120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 95605125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 653343600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 375366960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6480752940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7690505250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16926799275 # Total energy per rank (pJ) -system.physmem_1.averagePower 759.311692 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12714890500 # Time in different power states -system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8833037000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16464676 # Number of BP lookups -system.cpu.branchPred.condPredicted 10658312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 322373 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8884191 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7232535 # Number of BTB hits +system.physmem.busUtil 6.15 # Data bus utilization in percentage +system.physmem.busUtilRead 3.62 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 145971 # Number of row buffer hits during reads +system.physmem.writeRowHits 89923 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 81328.57 # Average gap between requests +system.physmem.pageHitRate 84.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153103020 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 81361005 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 582666840 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 298813680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1398920640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1820142240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 87895200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 2523555300 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1884269760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 2191410645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11023267740 # Total energy per rank (pJ) +system.physmem_0.averagePower 483.057740 # Core power per rank (mW) +system.physmem_0.totalIdleTime 18596850000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 135529000 # Time in different power states +system.physmem_0.memoryStateTime::REF 594334000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 8155766000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 4906976500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3493009750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 5534156250 # Time in different power states +system.physmem_1.actEnergy 165747960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 88078155 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 598167780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 302363280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1429652640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1911531480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 82258560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 2724848520 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1880202720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 2026371015 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11210189940 # Total energy per rank (pJ) +system.physmem_1.averagePower 491.248979 # Core power per rank (mW) +system.physmem_1.totalIdleTime 18411251500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 119903000 # Time in different power states +system.physmem_1.memoryStateTime::REF 607208000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 7539541250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 4896374750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3681289750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 5975454750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16458678 # Number of BP lookups +system.cpu.branchPred.condPredicted 10655092 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 320474 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8794743 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7227596 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.409044 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1975403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3321 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39323 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31540 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7783 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2655 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 82.180866 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1974394 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3324 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39317 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31522 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7795 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2656 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22505585 # DTB read hits -system.cpu.dtb.read_misses 226699 # DTB read misses +system.cpu.dtb.read_hits 22495361 # DTB read hits +system.cpu.dtb.read_misses 227004 # DTB read misses system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22732284 # DTB read accesses -system.cpu.dtb.write_hits 15808846 # DTB write hits -system.cpu.dtb.write_misses 44546 # DTB write misses +system.cpu.dtb.read_accesses 22722365 # DTB read accesses +system.cpu.dtb.write_hits 15803250 # DTB write hits +system.cpu.dtb.write_misses 44602 # DTB write misses system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15853392 # DTB write accesses -system.cpu.dtb.data_hits 38314431 # DTB hits -system.cpu.dtb.data_misses 271245 # DTB misses +system.cpu.dtb.write_accesses 15847852 # DTB write accesses +system.cpu.dtb.data_hits 38298611 # DTB hits +system.cpu.dtb.data_misses 271606 # DTB misses system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38585676 # DTB accesses -system.cpu.itb.fetch_hits 13724143 # ITB hits -system.cpu.itb.fetch_misses 29345 # ITB misses +system.cpu.dtb.data_accesses 38570217 # DTB accesses +system.cpu.itb.fetch_hits 13713928 # ITB hits +system.cpu.itb.fetch_misses 29641 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13753488 # ITB accesses +system.cpu.itb.fetch_accesses 13743569 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,101 +337,101 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44587088 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 45639548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15537600 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105003279 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16464676 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9239478 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27573681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 883330 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 330450 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13724143 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187041 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15527632 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104958165 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16458678 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9233512 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 28526394 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 879432 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1335 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 342280 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 91 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13713928 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 186437 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43888428 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.392505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 44842161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.340613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.113400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24387762 55.57% 55.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1515251 3.45% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1377134 3.14% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1500310 3.42% 65.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4190997 9.55% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1825571 4.16% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669926 1.53% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050385 2.39% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7371092 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25352844 56.54% 56.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1513864 3.38% 59.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1375551 3.07% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1499198 3.34% 66.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4186922 9.34% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1824752 4.07% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669001 1.49% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050081 2.34% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7369948 16.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43888428 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369270 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.355015 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14897050 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9776190 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18280655 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 589828 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 344705 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3701787 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98635 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103032848 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312916 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 344705 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15240775 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4552016 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97125 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18511621 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5142186 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102032260 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5895 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 92509 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 354670 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4626637 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61342957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123044735 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122725402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319332 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44842161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.360623 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.299720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14899514 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10738608 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18272960 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 588305 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 342774 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3699945 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98528 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 102994976 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312859 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 342774 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15240271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5029380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97820 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18506228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5625688 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102003977 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6871 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 88609 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 422499 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5043111 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61324692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123005722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122686459 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319262 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8796076 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5684 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5736 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2358572 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23134576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16358313 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246652 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 504576 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90719727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88603709 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68043 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11133526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4439018 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 973 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43888428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018840 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8777811 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5683 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5735 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2339310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23131891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16353716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1249387 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 502474 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90699211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88573949 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67838 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11113012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4439512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 975 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44842161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.975238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.240795 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17434377 39.72% 39.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5720394 13.03% 52.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5103914 11.63% 64.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4383916 9.99% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4317842 9.84% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2637316 6.01% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1940633 4.42% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378295 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 971741 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18402096 41.04% 41.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5711089 12.74% 53.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5105714 11.39% 65.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4382501 9.77% 74.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4313150 9.62% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2637224 5.88% 90.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1940283 4.33% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1377321 3.07% 97.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 972783 2.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43888428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44842161 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 241284 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 241463 9.57% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available @@ -449,19 +460,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1166228 46.24% 55.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1114848 44.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168337 46.29% 55.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1114013 44.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49379489 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44005 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49366935 55.74% 55.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43991 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121171 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120707 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39092 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -483,82 +494,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22899221 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15999870 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22887844 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15994084 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88603709 # Type of FU issued -system.cpu.iq.rate 1.987206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2522360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223074890 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101458980 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86835527 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420488 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299878 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90820238 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305831 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1672227 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued +system.cpu.iq.rate 1.940728 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523813 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028494 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223970382 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611328 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90791946 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305816 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2857938 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5878 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20874 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1744936 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5856 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20836 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3021 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 200758 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3017 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 190756 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 344705 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1315985 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2729229 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100214269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 118431 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23134576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16358313 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5556 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3898 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2727794 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20874 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113179 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 152389 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 265568 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87909421 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22732927 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 694288 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 342774 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1435868 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3107979 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100192818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 116708 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23131891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16353716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5558 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3773 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3106841 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20836 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 111267 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 152585 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 263852 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87883972 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22722991 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 689977 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9488986 # number of nop insts executed -system.cpu.iew.exec_refs 38586655 # number of memory reference insts executed -system.cpu.iew.exec_branches 15119960 # Number of branches executed -system.cpu.iew.exec_stores 15853728 # Number of stores executed -system.cpu.iew.exec_rate 1.971634 # Inst execution rate -system.cpu.iew.wb_sent 87537444 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87135405 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33842966 # num instructions producing a value -system.cpu.iew.wb_consumers 44247648 # num instructions consuming a value -system.cpu.iew.wb_rate 1.954274 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764853 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8653815 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9488049 # number of nop insts executed +system.cpu.iew.exec_refs 38571182 # number of memory reference insts executed +system.cpu.iew.exec_branches 15118040 # Number of branches executed +system.cpu.iew.exec_stores 15848191 # Number of stores executed +system.cpu.iew.exec_rate 1.925610 # Inst execution rate +system.cpu.iew.wb_sent 87519959 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87118018 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33843453 # num instructions producing a value +system.cpu.iew.wb_consumers 44250497 # num instructions consuming a value +system.cpu.iew.wb_rate 1.908827 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764815 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8632074 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 225413 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42617548 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.072871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.885939 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 223532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43575084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.027321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.870724 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21149374 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6281932 14.74% 64.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2908445 6.82% 71.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1738602 4.08% 75.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1681485 3.95% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1121192 2.63% 81.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1200701 2.82% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 796598 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5739219 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22117259 50.76% 50.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6277727 14.41% 65.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2900957 6.66% 71.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1737731 3.99% 75.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1677521 3.85% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1124025 2.58% 82.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1202727 2.76% 85.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795829 1.83% 86.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5741308 13.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42617548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43575084 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,471 +615,471 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5739219 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132555474 # The number of ROB reads -system.cpu.rob.rob_writes 195263120 # The number of ROB writes -system.cpu.timesIdled 45271 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 698660 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5741308 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 133489180 # The number of ROB reads +system.cpu.rob.rob_writes 195215826 # The number of ROB writes +system.cpu.timesIdled 45373 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 797387 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.560197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.560197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.785085 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.785085 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116363135 # number of integer regfile reads -system.cpu.int_regfile_writes 57669565 # number of integer regfile writes -system.cpu.fp_regfile_reads 255561 # number of floating regfile reads -system.cpu.fp_regfile_writes 240404 # number of floating regfile writes -system.cpu.misc_regfile_reads 38263 # number of misc regfile reads +system.cpu.cpi 0.573421 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.573421 # CPI: Total CPI of All Threads +system.cpu.ipc 1.743921 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.743921 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116327818 # number of integer regfile reads +system.cpu.int_regfile_writes 57658172 # number of integer regfile writes +system.cpu.fp_regfile_reads 255578 # number of floating regfile reads +system.cpu.fp_regfile_writes 240399 # number of floating regfile writes +system.cpu.misc_regfile_reads 38260 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201400 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.443451 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33984025 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205496 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.375603 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 232048500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.443451 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993761 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 201413 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.948439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33978122 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205509 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.336418 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244590500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.948439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993640 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2488 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1533 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70817108 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70817108 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20422994 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20422994 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13560978 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13560978 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33983972 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33983972 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33983972 # number of overall hits -system.cpu.dcache.overall_hits::total 33983972 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269382 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269382 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052399 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052399 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321781 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321781 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321781 # number of overall misses -system.cpu.dcache.overall_misses::total 1321781 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18043068500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18043068500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88421559159 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88421559159 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106464627659 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106464627659 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106464627659 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106464627659 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20692376 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20692376 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70808789 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70808789 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20418812 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20418812 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13559258 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13559258 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33978070 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33978070 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33978070 # number of overall hits +system.cpu.dcache.overall_hits::total 33978070 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269399 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269399 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1054119 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1054119 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1323518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1323518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1323518 # number of overall misses +system.cpu.dcache.overall_misses::total 1323518 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19371317500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19371317500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 94432641988 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 94432641988 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113803959488 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113803959488 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113803959488 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113803959488 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20688211 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20688211 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35305753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35305753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35305753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35305753 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072016 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072016 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037438 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037438 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037438 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037438 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80546.344409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80546.344409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6874865 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 86609 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35301588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35301588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35301588 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35301588 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072134 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072134 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037492 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037492 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037492 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037492 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85985.955225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85985.955225 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7415690 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 299 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 82797 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.378182 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 139.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168502 # number of writebacks -system.cpu.dcache.writebacks::total 168502 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207279 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207279 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 909006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 909006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1116285 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1116285 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1116285 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1116285 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205496 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205496 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205496 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205496 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3336459000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3336459000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14128429272 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14128429272 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17464888272 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17464888272 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17464888272 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17464888272 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005820 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005820 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90436 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.490065 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13619166 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92484 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.259699 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18779712500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.490065 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935786 # Average percentage of cache occupancy +system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.564719 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 149.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168510 # number of writebacks +system.cpu.dcache.writebacks::total 168510 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207284 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207284 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910725 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910725 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1118009 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1118009 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1118009 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1118009 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62115 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62115 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205509 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205509 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205509 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205509 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3617431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3617431500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15283982713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15283982713 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18901414213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18901414213 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18901414213 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18901414213 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005822 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005822 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58237.647911 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58237.647911 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106587.323828 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106587.323828 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 90457 # number of replacements +system.cpu.icache.tags.tagsinuse 1914.919853 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13608920 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92505 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.115507 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19216549500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1914.919853 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935019 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935019 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1460 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 389 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1462 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27540768 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27540768 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13619166 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13619166 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13619166 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13619166 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13619166 # number of overall hits -system.cpu.icache.overall_hits::total 13619166 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 104976 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 104976 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 104976 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 104976 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 104976 # number of overall misses -system.cpu.icache.overall_misses::total 104976 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1956506499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1956506499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1956506499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1956506499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1956506499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1956506499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13724142 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13724142 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13724142 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13724142 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13724142 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13724142 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007649 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007649 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007649 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007649 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007649 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007649 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18637.655264 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18637.655264 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18637.655264 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18637.655264 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18637.655264 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18637.655264 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1136 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27520357 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27520357 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 13608920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13608920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13608920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13608920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13608920 # number of overall hits +system.cpu.icache.overall_hits::total 13608920 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105006 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105006 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105006 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105006 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105006 # number of overall misses +system.cpu.icache.overall_misses::total 105006 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2088801499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2088801499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2088801499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2088801499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2088801499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2088801499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13713926 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13713926 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13713926 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13713926 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13713926 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13713926 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007657 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007657 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007657 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007657 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007657 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007657 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19892.210912 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19892.210912 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19892.210912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19892.210912 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 683 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 75.733333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.687500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 90436 # number of writebacks -system.cpu.icache.writebacks::total 90436 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12491 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12491 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12491 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12491 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12491 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12491 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92485 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 92485 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 92485 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 92485 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 92485 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 92485 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1595124000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1595124000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1595124000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1595124000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1595124000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1595124000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006739 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006739 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006739 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006739 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006739 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006739 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17247.380656 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17247.380656 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17247.380656 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17247.380656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17247.380656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17247.380656 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 134874 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31863.975507 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 422062 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 167642 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.517639 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4859656000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 722.364840 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1777.470792 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29364.139876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.022045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054244 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.896122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.972411 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 90457 # number of writebacks +system.cpu.icache.writebacks::total 90457 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12500 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12500 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12500 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12500 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12500 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12500 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92506 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 92506 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 92506 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 92506 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 92506 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 92506 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1693618500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1693618500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1693618500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1693618500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1693618500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1693618500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006745 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006745 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006745 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18308.201630 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18308.201630 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 134872 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31840.102351 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 422133 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 167640 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.518092 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5003072000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 716.868966 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1773.767441 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29349.465945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.021877 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054131 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.895675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.971683 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2938 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 29364 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 202 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2733 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28770 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1005 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4886178 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4886178 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168502 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168502 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 90436 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 90436 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12584 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12584 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86017 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 86017 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33990 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33990 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86017 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46574 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132591 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86017 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46574 # number of overall hits -system.cpu.l2cache.overall_hits::total 132591 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130811 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130811 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6468 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6468 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28111 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28111 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6468 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158922 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165390 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6468 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158922 # number of overall misses -system.cpu.l2cache.overall_misses::total 165390 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13777150000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13777150000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 548837500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 548837500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2881866500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2881866500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 548837500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16659016500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17207854000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 548837500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16659016500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17207854000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168502 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168502 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 90436 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 90436 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143395 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143395 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92485 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 92485 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62101 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 62101 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 92485 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205496 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 297981 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 92485 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205496 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 297981 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912242 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912242 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069936 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069936 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452666 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452666 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069936 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773358 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.555035 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069936 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773358 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.555035 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105321.035693 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105321.035693 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84854.282622 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84854.282622 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102517.395326 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102517.395326 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 104044.101820 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 104044.101820 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 4886720 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4886720 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 168510 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168510 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 90457 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 90457 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12581 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12581 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86036 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 86036 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34007 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 34007 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46588 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132624 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86036 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46588 # number of overall hits +system.cpu.l2cache.overall_hits::total 132624 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130815 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130815 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6470 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6470 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28106 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28106 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6470 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158921 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165391 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6470 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158921 # number of overall misses +system.cpu.l2cache.overall_misses::total 165391 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14933033000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14933033000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 647096000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 647096000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3162742000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3162742000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 647096000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18095775000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18742871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 647096000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18095775000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18742871000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168510 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168510 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 90457 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 90457 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143396 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143396 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92506 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 92506 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62113 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 62113 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 92506 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205509 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 298015 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 92506 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205509 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 298015 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912264 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912264 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069941 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069941 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452498 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452498 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069941 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773304 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.554975 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069941 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773304 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.554975 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 114153.827925 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 114153.827925 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100014.837713 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100014.837713 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112529.068526 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112529.068526 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 113324.612585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 113324.612585 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115201 # number of writebacks -system.cpu.l2cache.writebacks::total 115201 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130811 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130811 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6468 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6468 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28111 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28111 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158922 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165390 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6468 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158922 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165390 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12469040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12469040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 484167500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 484167500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2600756500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2600756500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 484167500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15069796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15553964000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 484167500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15069796500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15553964000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 115198 # number of writebacks +system.cpu.l2cache.writebacks::total 115198 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130815 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130815 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6470 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6470 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28106 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28106 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158921 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165391 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6470 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158921 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165391 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13624883000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13624883000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 582406000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 582406000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2881682000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2881682000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 582406000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16506565000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17088971000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 582406000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16506565000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17088971000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452666 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452666 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589817 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291836 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912264 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912264 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452498 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452498 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.554975 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.554975 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589885 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291870 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4239 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4237 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4237 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887797 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11706880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23935872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35642752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134874 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7372864 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 432855 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009793 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098475 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 154618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62113 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275468 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612431 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11709568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23937216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35646784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134872 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7372672 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 432887 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098448 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 428616 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4239 0.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428650 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4237 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432855 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553846500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138734483 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432887 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553909500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 138764985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308248491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308272981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130746 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_requests 130745 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34578 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115200 # Transaction distribution -system.membus.trans_dist::CleanEvict 15546 # Transaction distribution -system.membus.trans_dist::ReadExReq 130811 # Transaction distribution -system.membus.trans_dist::ReadExResp 130811 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34578 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 461524 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17957696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34575 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115197 # Transaction distribution +system.membus.trans_dist::CleanEvict 15548 # Transaction distribution +system.membus.trans_dist::ReadExReq 130815 # Transaction distribution +system.membus.trans_dist::ReadExResp 130815 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 461525 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17957568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165389 # Request fanout histogram +system.membus.snoop_fanout::samples 165390 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165390 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165389 # Request fanout histogram -system.membus.reqLayer0.occupancy 780841500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 854544750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.8 # Layer utilization (%) +system.membus.snoop_fanout::total 165390 # Request fanout histogram +system.membus.reqLayer0.occupancy 779827500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 851966000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- |