diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/se/50.vortex/ref/alpha | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha')
4 files changed, 827 insertions, 827 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 8786d03ec..a906c40f3 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:15:15 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:38:51 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 46914279500 because target called exit() +Exiting @ tick 47232621500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 22fcb32bd..447e68abd 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046914 # Number of seconds simulated -sim_ticks 46914279500 # Number of ticks simulated -final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047233 # Number of seconds simulated +sim_ticks 47232621500 # Number of ticks simulated +final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145791 # Simulator instruction rate (inst/s) -host_op_rate 145791 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77424105 # Simulator tick rate (ticks/s) -host_mem_usage 218104 # Number of bytes of host memory used -host_seconds 605.94 # Real time elapsed on the host +host_inst_rate 142426 # Simulator instruction rate (inst/s) +host_op_rate 142426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76149893 # Simulator tick rate (ticks/s) +host_mem_usage 218108 # Number of bytes of host memory used +host_seconds 620.26 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11164096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7712960 # Number of bytes written to this memory -system.physmem.num_reads 174439 # Number of read requests responded to by this memory -system.physmem.num_writes 120515 # Number of write requests responded to by this memory +system.physmem.bytes_read 11167232 # Number of bytes read from this memory +system.physmem.bytes_inst_read 602240 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7713024 # Number of bytes written to this memory +system.physmem.num_reads 174488 # Number of read requests responded to by this memory +system.physmem.num_writes 120516 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 236430493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 12750510 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 163298664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 399729158 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277222 # DTB read hits +system.cpu.dtb.read_hits 20277221 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367370 # DTB read accesses +system.cpu.dtb.read_accesses 20367369 # DTB read accesses system.cpu.dtb.write_hits 14736811 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 14744063 # DTB write accesses -system.cpu.dtb.data_hits 35014033 # DTB hits +system.cpu.dtb.data_hits 35014032 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111433 # DTB accesses -system.cpu.itb.fetch_hits 12380499 # ITB hits -system.cpu.itb.fetch_misses 10576 # ITB misses +system.cpu.dtb.data_accesses 35111432 # DTB accesses +system.cpu.itb.fetch_hits 12477897 # ITB hits +system.cpu.itb.fetch_misses 13095 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12391075 # ITB accesses +system.cpu.itb.fetch_accesses 12490992 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 93828560 # number of cpu cycles simulated +system.cpu.numCycles 94465244 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed. -system.cpu.activity 74.177435 # Percentage of cycles cpu is active +system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed. +system.cpu.activity 74.400368 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target. +system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16222590 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5048183 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660950 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.118231 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8476014 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10352977 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74323677 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126642927 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65289 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35053135 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292919 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14127497 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064147 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4680877 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233308 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4914185 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8858001 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.681953 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 83610 # number of replacements -system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use -system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51809989 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42655255 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.154443 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 51339314 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43125930 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.652695 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 72336276 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22128968 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.425513 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 48368266 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46096978 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.797818 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85310 # number of replacements +system.cpu.icache.tagsinuse 1887.040544 # Cycle average of tags in use +system.cpu.icache.total_refs 12359577 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87356 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.485153 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1886.858130 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921317 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921317 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12263478 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12263478 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12263478 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12263478 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12263478 # number of overall hits -system.cpu.icache.overall_hits::total 12263478 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 116984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 116984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 116984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 116984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 116984 # number of overall misses -system.cpu.icache.overall_misses::total 116984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2068004000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2068004000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2068004000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2068004000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2068004000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12380462 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12380462 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12380462 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12380462 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12380462 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.665322 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1887.040544 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.921407 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.921407 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12359577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12359577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12359577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12359577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12359577 # number of overall hits +system.cpu.icache.overall_hits::total 12359577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118263 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118263 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118263 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118263 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118263 # number of overall misses +system.cpu.icache.overall_misses::total 118263 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2089534000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2089534000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2089534000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2089534000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2089534000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2089534000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12477840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12477840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12477840 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12477840 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12477840 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12477840 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009478 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009478 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1485500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 122 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 12176.229508 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 31328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 31328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 31328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 31328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 85656 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 85656 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 85656 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 85656 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 85656 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1345401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1345401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1345401500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15707.031615 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30907 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30907 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30907 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30907 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30907 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30907 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87356 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87356 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87356 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1366128500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1366128500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1366128500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1366128500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.126583 # Cycle average of tags in use +system.cpu.dcache.total_refs 34125996 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.105766 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994411 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180445 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945569 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126014 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126014 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34126014 # number of overall hits -system.cpu.dcache.overall_hits::total 34126014 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96193 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96193 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667808 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667808 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 764001 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 764001 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 764001 # number of overall misses -system.cpu.dcache.overall_misses::total 764001 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4158649000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35332073000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39490722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39490722000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39490722000 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000230 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4073.126583 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994416 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994416 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180455 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180455 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945541 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34125996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34125996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34125996 # number of overall hits +system.cpu.dcache.overall_hits::total 34125996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667836 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667836 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764019 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764019 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764019 # number of overall misses +system.cpu.dcache.overall_misses::total 764019 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4158611000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4158611000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35328865500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35328865500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39487476500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39487476500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39487476500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39487476500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 34890015 # nu system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43232.345389 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52907.531806 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43236.445110 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52900.510754 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124110 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50998.561760 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161216 # number of writebacks -system.cpu.dcache.writebacks::total 161216 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35426 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35426 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524228 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559654 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559654 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 161215 # number of writebacks +system.cpu.dcache.writebacks::total 161215 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35416 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524256 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524256 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559672 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -269,98 +269,98 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088724500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088724500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254420000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343144500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9343144500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343144500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9343144500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088876000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088876000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254482000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254482000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343358000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148060 # number of replacements -system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use -system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 148111 # number of replacements +system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use +system.cpu.l2cache.total_refs 132979 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 173456 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.766644 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15657.764606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1362.413436 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1643.378886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.477837 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.041578 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.050152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.569567 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 76292 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 27002 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 103294 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 161216 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161216 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 15657.217235 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1374.269041 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1640.204088 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.477820 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.041939 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.050055 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.569815 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 77946 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 26999 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 104945 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 161215 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 161215 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 76292 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39272 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 115564 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 489614500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8607077000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9096691500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 489614500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8607077000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9096691500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 85656 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 9410 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 165078 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174488 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9410 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 165078 # number of overall misses +system.cpu.l2cache.overall_misses::total 174488 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 492013000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752923000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2244936000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854378000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6854378000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 492013000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8607301000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9099314000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 492013000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8607301000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9099314000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 87356 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146233 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 161216 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 161216 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 147933 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 161215 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 161215 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 85656 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 87356 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290003 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 85656 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 291703 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 87356 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290003 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.109321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554253 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109321 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.807817 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109321 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.807817 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,44 +369,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120515 # number of writebacks -system.cpu.l2cache.writebacks::total 120515 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9364 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33575 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 42939 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 120516 # number of writebacks +system.cpu.l2cache.writebacks::total 120516 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9410 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 42988 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9364 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 165075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9364 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 165075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 174439 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 375279000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343349500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1718628500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262711000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262711000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 375279000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606060500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6981339500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 375279000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606060500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6981339500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554253 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9410 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 165078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9410 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 165078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 377128500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343464000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1720592500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262752500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262752500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 377128500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606216500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6983345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 377128500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 8276bb368..4f0567259 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:19:29 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:42:57 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21259532000 because target called exit() +Exiting @ tick 21302882000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index a0babad48..3e4315992 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021260 # Number of seconds simulated -sim_ticks 21259532000 # Number of ticks simulated -final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021303 # Number of seconds simulated +sim_ticks 21302882000 # Number of ticks simulated +final_tick 21302882000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240617 # Simulator instruction rate (inst/s) -host_op_rate 240617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64270421 # Simulator tick rate (ticks/s) -host_mem_usage 219780 # Number of bytes of host memory used -host_seconds 330.78 # Real time elapsed on the host +host_inst_rate 238426 # Simulator instruction rate (inst/s) +host_op_rate 238426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63815052 # Simulator tick rate (ticks/s) +host_mem_usage 219800 # Number of bytes of host memory used +host_seconds 333.82 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11229312 # Number of bytes read from this memory -system.physmem.bytes_inst_read 642688 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7713344 # Number of bytes written to this memory -system.physmem.num_reads 175458 # Number of read requests responded to by this memory -system.physmem.num_writes 120521 # Number of write requests responded to by this memory +system.physmem.bytes_read 11250368 # Number of bytes read from this memory +system.physmem.bytes_inst_read 658624 # Number of instructions bytes read from this memory +system.physmem.bytes_written 7713792 # Number of bytes written to this memory +system.physmem.num_reads 175787 # Number of read requests responded to by this memory +system.physmem.num_writes 120528 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 528201279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 30230581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 362818147 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 891019426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 528114834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 30917131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 362100865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 890215699 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22309038 # DTB read hits -system.cpu.dtb.read_misses 216523 # DTB read misses -system.cpu.dtb.read_acv 41 # DTB read access violations -system.cpu.dtb.read_accesses 22525561 # DTB read accesses -system.cpu.dtb.write_hits 15629688 # DTB write hits -system.cpu.dtb.write_misses 39366 # DTB write misses -system.cpu.dtb.write_acv 9 # DTB write access violations -system.cpu.dtb.write_accesses 15669054 # DTB write accesses -system.cpu.dtb.data_hits 37938726 # DTB hits -system.cpu.dtb.data_misses 255889 # DTB misses -system.cpu.dtb.data_acv 50 # DTB access violations -system.cpu.dtb.data_accesses 38194615 # DTB accesses -system.cpu.itb.fetch_hits 13877051 # ITB hits -system.cpu.itb.fetch_misses 28133 # ITB misses +system.cpu.dtb.read_hits 22551743 # DTB read hits +system.cpu.dtb.read_misses 221888 # DTB read misses +system.cpu.dtb.read_acv 31 # DTB read access violations +system.cpu.dtb.read_accesses 22773631 # DTB read accesses +system.cpu.dtb.write_hits 15815895 # DTB write hits +system.cpu.dtb.write_misses 41880 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 15857775 # DTB write accesses +system.cpu.dtb.data_hits 38367638 # DTB hits +system.cpu.dtb.data_misses 263768 # DTB misses +system.cpu.dtb.data_acv 34 # DTB access violations +system.cpu.dtb.data_accesses 38631406 # DTB accesses +system.cpu.itb.fetch_hits 14242802 # ITB hits +system.cpu.itb.fetch_misses 40881 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13905184 # ITB accesses +system.cpu.itb.fetch_accesses 14283683 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,247 +54,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42519067 # number of cpu cycles simulated +system.cpu.numCycles 42605767 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16615602 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10784809 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 464390 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14543138 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8570194 # Number of BTB hits +system.cpu.BPredUnit.lookups 16836861 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10841966 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 504890 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12277416 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7519870 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1986002 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 35485 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14905140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105779121 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16615602 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10556196 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20616414 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2026173 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4867777 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 282637 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 13877051 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 219292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42124503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.511107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.106328 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2023035 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 69381 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15349105 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 107382964 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16836861 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9542905 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19934365 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2235712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4959568 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 326008 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14242802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 231176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42192824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.545053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21508089 51.06% 51.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2128231 5.05% 56.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1654689 3.93% 60.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2031982 4.82% 64.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3913911 9.29% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1970832 4.68% 78.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 733979 1.74% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1130432 2.68% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7052358 16.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22258459 52.75% 52.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1558399 3.69% 56.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1415455 3.35% 59.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1535754 3.64% 63.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4212607 9.98% 73.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1888173 4.48% 77.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 696328 1.65% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1104060 2.62% 82.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7523589 17.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42124503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.390780 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.487804 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15964361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4443062 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19692488 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 675645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1348947 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3728678 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99733 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103933078 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 280329 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1348947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16452599 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2364451 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84031 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19835916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2038559 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102562493 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 192 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2676 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1925408 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61709040 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123636906 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123159992 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 476914 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42192824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.395178 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.520386 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16468277 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4517812 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18984446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 716137 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1506152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3833098 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 111400 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 105432186 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305241 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1506152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16967340 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2377848 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 83482 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19155996 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2102006 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103893842 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 209 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2243 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1985062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62645887 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 125253216 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124792086 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 461130 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9162159 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5460 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4149992 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23138107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16243401 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1017520 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 376699 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90712605 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5415 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88293060 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101013 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10834162 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4923026 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 832 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42124503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.096002 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.077334 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10099006 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6339 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6334 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4415607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23483376 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16437713 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1109953 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 422268 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91768592 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5634 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89301611 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 133191 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11574502 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5080166 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1051 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42192824 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.116512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.120688 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13300851 31.58% 31.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7326403 17.39% 48.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5817137 13.81% 62.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4863957 11.55% 74.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4880067 11.58% 85.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2467879 5.86% 91.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1850711 4.39% 96.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1163401 2.76% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 454097 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13823160 32.76% 32.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6872678 16.29% 49.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5530993 13.11% 62.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4799446 11.38% 73.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4794506 11.36% 84.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2657744 6.30% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1943834 4.61% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1324843 3.14% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 445620 1.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42124503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42192824 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 99927 5.41% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 762620 41.31% 46.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 983690 53.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129735 6.85% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 797111 42.11% 48.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 966009 51.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49334128 55.88% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44107 0.05% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 126794 0.14% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 90 0.00% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 127284 0.14% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38913 0.04% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22763265 25.78% 82.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15858425 17.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49865595 55.84% 55.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121283 0.14% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121847 0.14% 56.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38973 0.04% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23075616 25.84% 82.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16034269 17.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88293060 # Type of FU issued -system.cpu.iq.rate 2.076552 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1846238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020910 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 220034609 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101108296 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86316001 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 623265 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 459484 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 302223 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89827554 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 311744 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1421900 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89301611 # Type of FU issued +system.cpu.iq.rate 2.095998 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1892856 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021196 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222206616 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102943544 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87154270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615477 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 421862 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299078 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90886504 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307963 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1459837 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2861469 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4255 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15998 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1630024 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3206738 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5121 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17710 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1824336 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1348947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1395228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 60292 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100209488 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 330917 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23138107 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16243401 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5415 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 717 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 15998 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 305754 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 116766 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 422520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87324044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22528336 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 969016 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1506152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1422947 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 61908 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101335985 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 260919 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23483376 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16437713 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5634 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42556 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17710 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 285901 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 175983 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 461884 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88268407 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22778571 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1033204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9491468 # number of nop insts executed -system.cpu.iew.exec_refs 38197877 # number of memory reference insts executed -system.cpu.iew.exec_branches 15069707 # Number of branches executed -system.cpu.iew.exec_stores 15669541 # Number of stores executed -system.cpu.iew.exec_rate 2.053762 # Inst execution rate -system.cpu.iew.wb_sent 87015038 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86618224 # cumulative count of insts written-back -system.cpu.iew.wb_producers 32981280 # num instructions producing a value -system.cpu.iew.wb_consumers 42978824 # num instructions consuming a value +system.cpu.iew.exec_nop 9561759 # number of nop insts executed +system.cpu.iew.exec_refs 38636897 # number of memory reference insts executed +system.cpu.iew.exec_branches 15172966 # Number of branches executed +system.cpu.iew.exec_stores 15858326 # Number of stores executed +system.cpu.iew.exec_rate 2.071748 # Inst execution rate +system.cpu.iew.wb_sent 87882567 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87453348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33493281 # num instructions producing a value +system.cpu.iew.wb_consumers 43663372 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.037162 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767384 # average fanout of values written-back +system.cpu.iew.wb_rate 2.052618 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767080 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8835054 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9892654 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 366565 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40775556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.166511 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804904 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396008 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40686672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.171243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.822339 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17645835 43.28% 43.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7080138 17.36% 60.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3592753 8.81% 69.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2169640 5.32% 74.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2013725 4.94% 79.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1230420 3.02% 82.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1128970 2.77% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727312 1.78% 87.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5186763 12.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17747243 43.62% 43.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7065292 17.37% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3424426 8.42% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2111790 5.19% 74.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2029147 4.99% 79.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1183341 2.91% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1120057 2.75% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 705485 1.73% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5299891 13.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40775556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40686672 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -305,64 +305,64 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5186763 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5299891 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131447177 # The number of ROB reads -system.cpu.rob.rob_writes 195703293 # The number of ROB writes -system.cpu.timesIdled 15923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 394564 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132302765 # The number of ROB reads +system.cpu.rob.rob_writes 197976180 # The number of ROB writes +system.cpu.timesIdled 17931 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 412943 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.534214 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534214 # CPI: Total CPI of All Threads -system.cpu.ipc 1.871907 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.871907 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115518864 # number of integer regfile reads -system.cpu.int_regfile_writes 57354047 # number of integer regfile writes -system.cpu.fp_regfile_reads 252314 # number of floating regfile reads -system.cpu.fp_regfile_writes 251108 # number of floating regfile writes -system.cpu.misc_regfile_reads 38108 # number of misc regfile reads +system.cpu.cpi 0.535304 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.535304 # CPI: Total CPI of All Threads +system.cpu.ipc 1.868098 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.868098 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116852046 # number of integer regfile reads +system.cpu.int_regfile_writes 57987678 # number of integer regfile writes +system.cpu.fp_regfile_reads 254259 # number of floating regfile reads +system.cpu.fp_regfile_writes 241396 # number of floating regfile writes +system.cpu.misc_regfile_reads 38319 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 88378 # number of replacements -system.cpu.icache.tagsinuse 1927.638696 # Cycle average of tags in use -system.cpu.icache.total_refs 13782143 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 90426 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152.413498 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17839872000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1927.638696 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13782143 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13782143 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13782143 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13782143 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13782143 # number of overall hits -system.cpu.icache.overall_hits::total 13782143 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 94908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 94908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 94908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 94908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 94908 # number of overall misses -system.cpu.icache.overall_misses::total 94908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 914028500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 914028500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 914028500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 914028500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 914028500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 914028500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13877051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13877051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13877051 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13877051 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13877051 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13877051 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006839 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006839 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006839 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9630.679184 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9630.679184 # average overall miss latency +system.cpu.icache.replacements 94879 # number of replacements +system.cpu.icache.tagsinuse 1931.404224 # Cycle average of tags in use +system.cpu.icache.total_refs 14141018 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 96927 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 145.893487 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17852736000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1931.404224 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.943068 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.943068 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14141018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14141018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14141018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14141018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14141018 # number of overall hits +system.cpu.icache.overall_hits::total 14141018 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34409704 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34409704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34409704 # number of overall hits +system.cpu.dcache.overall_hits::total 34409704 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 257782 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 257782 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1035213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1035213 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1292995 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1292995 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1292995 # 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average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32865.120027 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32715.845767 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 96500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6433.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161613 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 120528 # number of writebacks +system.cpu.l2cache.writebacks::total 120528 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34099 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 44390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131397 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131397 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 319907000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176426000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5496333000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 319907000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176426000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5496333000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.546932 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916086 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.804241 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31086.094646 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.147658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.343410 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31086.094646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31278.254459 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |