diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/se/50.vortex/ref/alpha | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha')
4 files changed, 1244 insertions, 1175 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 57d7475f8..a8bf58a9c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,84 +1,84 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058327 # Number of seconds simulated -sim_ticks 58326668000 # Number of ticks simulated -final_tick 58326668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058385 # Number of seconds simulated +sim_ticks 58384546000 # Number of ticks simulated +final_tick 58384546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 319236 # Simulator instruction rate (inst/s) -host_op_rate 319236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210542764 # Simulator tick rate (ticks/s) -host_mem_usage 275532 # Number of bytes of host memory used -host_seconds 277.03 # Real time elapsed on the host +host_inst_rate 341517 # Simulator instruction rate (inst/s) +host_op_rate 341516 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 225460414 # Simulator tick rate (ticks/s) +host_mem_usage 300016 # Number of bytes of host memory used +host_seconds 258.96 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 10663104 # Number of bytes read from this memory system.physmem.bytes_read::total 10663104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 166611 # Number of read requests responded to by this memory system.physmem.num_reads::total 166611 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 182816958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182816958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8838496 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8838496 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 125141248 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 125141248 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 125141248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 182816958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 307958205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 182635727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182635727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8826445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8826445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 125017192 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 125017192 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 125017192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182635727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 307652919 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 166611 # Number of read requests accepted system.physmem.writeReqs 114048 # Number of write requests accepted system.physmem.readBursts 166611 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 10662592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297152 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10663104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10470 # Per bank write bursts -system.physmem.perBankRdBursts::1 10514 # Per bank write bursts +system.physmem.perBankRdBursts::0 10468 # Per bank write bursts +system.physmem.perBankRdBursts::1 10513 # Per bank write bursts system.physmem.perBankRdBursts::2 10311 # Per bank write bursts -system.physmem.perBankRdBursts::3 10091 # Per bank write bursts -system.physmem.perBankRdBursts::4 10432 # Per bank write bursts +system.physmem.perBankRdBursts::3 10090 # Per bank write bursts +system.physmem.perBankRdBursts::4 10431 # Per bank write bursts system.physmem.perBankRdBursts::5 10426 # Per bank write bursts -system.physmem.perBankRdBursts::6 9845 # Per bank write bursts -system.physmem.perBankRdBursts::7 10300 # Per bank write bursts +system.physmem.perBankRdBursts::6 9846 # Per bank write bursts +system.physmem.perBankRdBursts::7 10302 # Per bank write bursts system.physmem.perBankRdBursts::8 10593 # Per bank write bursts system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10596 # Per bank write bursts +system.physmem.perBankRdBursts::10 10595 # Per bank write bursts system.physmem.perBankRdBursts::11 10255 # Per bank write bursts system.physmem.perBankRdBursts::12 10302 # Per bank write bursts system.physmem.perBankRdBursts::13 10651 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10648 # Per bank write bursts +system.physmem.perBankRdBursts::15 10649 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6999 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::5 7178 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::7 7079 # Per bank write bursts +system.physmem.perBankWrBursts::8 7222 # Per bank write bursts system.physmem.perBankWrBursts::9 6940 # Per bank write bursts -system.physmem.perBankWrBursts::10 7095 # Per bank write bursts +system.physmem.perBankWrBursts::10 7097 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6965 # Per bank write bursts +system.physmem.perBankWrBursts::12 6967 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58326641500 # Total gap between requests +system.physmem.totGap 58384519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 114048 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 164957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -189,70 +189,68 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.133809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.314569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.108035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19364 35.49% 35.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11887 21.79% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5658 10.37% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3635 6.66% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2734 5.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2059 3.77% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1592 2.92% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1526 2.80% 88.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6108 11.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 54365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.333707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.729973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.976327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19356 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11696 21.51% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5632 10.36% 67.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3623 6.66% 74.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2688 4.94% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2044 3.76% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1686 3.10% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1497 2.75% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6143 11.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54365 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.733438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.155819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.733295 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.126500 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 7019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.244052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.228462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.746507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6270 89.33% 89.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.16% 89.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 572 8.15% 97.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 129 1.84% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.244194 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.228515 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.751123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6265 89.26% 89.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.26% 89.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 572 8.15% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 131 1.87% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.34% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 7019 # Writes before turning the bus around for reads -system.physmem.totQLat 1962392500 # Total ticks spent queuing -system.physmem.totMemAccLat 5086236250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11778.71 # Average queueing delay per DRAM burst +system.physmem.totQLat 2006026500 # Total ticks spent queuing +system.physmem.totMemAccLat 5129832750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833015000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12040.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30528.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 182.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 125.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 125.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30790.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 182.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 124.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 125.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.41 # Data bus utilization in percentage +system.physmem.busUtil 2.40 # Data bus utilization in percentage system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing -system.physmem.readRowHits 144808 # Number of row buffer hits during reads -system.physmem.writeRowHits 81240 # Number of row buffer hits during writes +system.physmem.avgWrQLen 23.87 # Average write queue length when enqueuing +system.physmem.readRowHits 144815 # Number of row buffer hits during reads +system.physmem.writeRowHits 81433 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes -system.physmem.avgGap 207820.31 # Average gap between requests -system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 31774168500 # Time in different power states -system.physmem.memoryStateTime::REF 1947400000 # Time in different power states +system.physmem.writeRowHitRate 71.40 # Row buffer hit rate for writes +system.physmem.avgGap 208026.54 # Average gap between requests +system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 31935315750 # Time in different power states +system.physmem.memoryStateTime::REF 1949480000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24597717750 # Time in different power states +system.physmem.memoryStateTime::ACT 24496780500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 307958205 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 35730 # Transaction distribution system.membus.trans_dist::ReadResp 35730 # Transaction distribution system.membus.trans_dist::Writeback 114048 # Transaction distribution @@ -260,44 +258,53 @@ system.membus.trans_dist::ReadExReq 130881 # Tr system.membus.trans_dist::ReadExResp 130881 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447270 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 447270 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17962176 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1302233000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 280659 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 280659 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 280659 # Request fanout histogram +system.membus.reqLayer0.occupancy 1302108500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1600678750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1600532000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14594840 # Number of BP lookups -system.cpu.branchPred.condPredicted 9449166 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 378473 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10265774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368296 # Number of BTB hits +system.cpu.branchPred.lookups 14593516 # Number of BP lookups +system.cpu.branchPred.condPredicted 9448617 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 379109 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10302575 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6369350 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.034251 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1700711 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 73330 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.822894 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1700742 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 73233 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20553993 # DTB read hits -system.cpu.dtb.read_misses 96885 # DTB read misses +system.cpu.dtb.read_hits 20554145 # DTB read hits +system.cpu.dtb.read_misses 96857 # DTB read misses system.cpu.dtb.read_acv 9 # DTB read access violations -system.cpu.dtb.read_accesses 20650878 # DTB read accesses -system.cpu.dtb.write_hits 14665827 # DTB write hits -system.cpu.dtb.write_misses 9394 # DTB write misses +system.cpu.dtb.read_accesses 20651002 # DTB read accesses +system.cpu.dtb.write_hits 14666071 # DTB write hits +system.cpu.dtb.write_misses 9396 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675221 # DTB write accesses -system.cpu.dtb.data_hits 35219820 # DTB hits -system.cpu.dtb.data_misses 106279 # DTB misses +system.cpu.dtb.write_accesses 14675467 # DTB write accesses +system.cpu.dtb.data_hits 35220216 # DTB hits +system.cpu.dtb.data_misses 106253 # DTB misses system.cpu.dtb.data_acv 9 # DTB access violations -system.cpu.dtb.data_accesses 35326099 # DTB accesses -system.cpu.itb.fetch_hits 25536643 # ITB hits -system.cpu.itb.fetch_misses 5175 # ITB misses +system.cpu.dtb.data_accesses 35326469 # DTB accesses +system.cpu.itb.fetch_hits 25540027 # ITB hits +system.cpu.itb.fetch_misses 5176 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25541818 # ITB accesses +system.cpu.itb.fetch_accesses 25545203 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,70 +318,70 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 116653336 # number of cpu cycles simulated +system.cpu.numCycles 116769092 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1184863 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1185538 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.319040 # CPI: cycles per instruction -system.cpu.ipc 0.758127 # IPC: instructions per cycle -system.cpu.tickCycles 90780036 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25873300 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 152673 # number of replacements -system.cpu.icache.tags.tagsinuse 1933.703122 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25381921 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 154721 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 164.049618 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41483619250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1933.703122 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.944191 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.944191 # Average percentage of cache occupancy +system.cpu.cpi 1.320349 # CPI: cycles per instruction +system.cpu.ipc 0.757376 # IPC: instructions per cycle +system.cpu.tickCycles 90792552 # Number of cycles that the object actually ticked +system.cpu.idleCycles 25976540 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 153164 # number of replacements +system.cpu.icache.tags.tagsinuse 1933.730829 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25384814 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155212 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.549300 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 41528149250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1933.730829 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.944205 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.944205 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51228007 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51228007 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25381921 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25381921 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25381921 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25381921 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25381921 # number of overall hits -system.cpu.icache.overall_hits::total 25381921 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 154722 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 154722 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 154722 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 154722 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 154722 # number of overall misses -system.cpu.icache.overall_misses::total 154722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2515300997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2515300997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2515300997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2515300997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2515300997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2515300997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25536643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25536643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25536643 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25536643 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25536643 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25536643 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006059 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006059 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006059 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006059 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006059 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006059 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16256.905915 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16256.905915 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16256.905915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16256.905915 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51235266 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51235266 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25384814 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25384814 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25384814 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25384814 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25384814 # number of overall hits +system.cpu.icache.overall_hits::total 25384814 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155213 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155213 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155213 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155213 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155213 # number of overall misses +system.cpu.icache.overall_misses::total 155213 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2516319497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2516319497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2516319497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2516319497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2516319497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2516319497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25540027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25540027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25540027 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25540027 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25540027 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25540027 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006077 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006077 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006077 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006077 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006077 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006077 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16212.040854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16212.040854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16212.040854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16212.040854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16212.040854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16212.040854 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,81 +390,90 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154722 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 154722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 154722 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 154722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 154722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 154722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2202760003 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2202760003 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2202760003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2202760003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2202760003 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2202760003 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006059 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006059 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006059 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14236.889408 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14236.889408 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14236.889408 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14236.889408 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14236.889408 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14236.889408 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155213 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 155213 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 155213 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 155213 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155213 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155213 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2202806503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2202806503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2202806503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2202806503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2202806503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2202806503 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14192.152094 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14192.152094 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14192.152094 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14192.152094 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14192.152094 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14192.152094 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 579498078 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 216032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 216031 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143563 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309443 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887723 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9902144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 33800192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 33800192 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 432598500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 216522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143561 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310425 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578271 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 888696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9933568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33831232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 528614 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 528614 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 528614 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 432838000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233630997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234362497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343195750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343210750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.cpu.l2cache.tags.replacements 132688 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30472.596016 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 219541 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30473.454944 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 220028 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.332465 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.335421 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26246.298923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.297093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800973 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.929950 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26247.246790 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.208154 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.801002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128974 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.929976 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32075 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11966 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18841 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1029 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18838 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 112 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978851 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4533358 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4533358 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 180301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 180301 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168534 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168534 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 12682 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12682 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 192983 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 192983 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 192983 # number of overall hits -system.cpu.l2cache.overall_hits::total 192983 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 4537236 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4537236 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 180791 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 180791 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168531 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168531 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 12680 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12680 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 193471 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 193471 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 193471 # number of overall hits +system.cpu.l2cache.overall_hits::total 193471 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 35731 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 35731 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.inst 130881 # number of ReadExReq misses @@ -466,40 +482,40 @@ system.cpu.l2cache.demand_misses::cpu.inst 166612 # system.cpu.l2cache.demand_misses::total 166612 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 166612 # number of overall misses system.cpu.l2cache.overall_misses::total 166612 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2608847500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2608847500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9666752250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9666752250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12275599750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12275599750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12275599750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12275599750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 216032 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 216032 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168534 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168534 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143563 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 359595 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 359595 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 359595 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 359595 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165397 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.165397 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911662 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911662 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463332 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.463332 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463332 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.463332 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73013.559654 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73013.559654 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73859.095285 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73859.095285 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73677.764807 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73677.764807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73677.764807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73677.764807 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2608794250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2608794250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9709899750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9709899750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12318694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12318694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12318694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12318694000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 216522 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 216522 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168531 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168531 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 360083 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 360083 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 360083 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 360083 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911675 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911675 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462704 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.462704 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462704 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.462704 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73012.069352 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73012.069352 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74188.764985 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74188.764985 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73936.415144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73936.415144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73936.415144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73936.415144 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,95 +534,95 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 166612 system.cpu.l2cache.demand_mshr_misses::total 166612 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 166612 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 166612 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2155704000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2155704000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7981949750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7981949750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10137653750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10137653750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10137653750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10137653750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165397 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165397 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911662 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911662 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463332 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.463332 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463332 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.463332 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60331.476869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60331.476869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60986.313903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60986.313903 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60845.879949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60845.879949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60845.879949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60845.879949 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2155637750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2155637750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 8025242250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8025242250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10180880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10180880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10180880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10180880000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165022 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165022 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911675 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911675 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462704 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.462704 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462704 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.462704 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.622737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.622737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61317.091480 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61317.091480 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61105.322546 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61105.322546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61105.322546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61105.322546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200777 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.421073 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34597319 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204873 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.872028 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 200774 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.445438 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34597334 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204870 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.874574 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 644670250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.421073 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.445438 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.994005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 754 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 755 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3288 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70138517 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70138517 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20264045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20264045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 14333274 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333274 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 34597319 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34597319 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 34597319 # number of overall hits -system.cpu.dcache.overall_hits::total 34597319 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 89400 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89400 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 280103 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280103 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 369503 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369503 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 369503 # number of overall misses -system.cpu.dcache.overall_misses::total 369503 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4413515000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4413515000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20003600250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20003600250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 24417115250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24417115250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 24417115250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24417115250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20353445 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20353445 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70138572 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70138572 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20264067 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20264067 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 14333267 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333267 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 34597334 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34597334 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 34597334 # number of overall hits +system.cpu.dcache.overall_hits::total 34597334 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 89407 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89407 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 280110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280110 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 369517 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369517 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 369517 # number of overall misses +system.cpu.dcache.overall_misses::total 369517 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4423552750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4423552750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20095524250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20095524250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 24519077000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24519077000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 24519077000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24519077000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20353474 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20353474 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 34966822 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34966822 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 34966822 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34966822 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004392 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 34966851 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34966851 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 34966851 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34966851 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019168 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.010567 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010567 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.010567 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010567 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49368.176734 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49368.176734 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71415.158888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71415.158888 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66080.966190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66080.966190 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.010568 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010568 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.010568 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010568 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49476.581811 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49476.581811 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71741.545286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71741.545286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66354.395062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66354.395062 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,32 +631,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168534 # number of writebacks -system.cpu.dcache.writebacks::total 168534 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28089 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28089 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136541 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 164630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 164630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164630 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61311 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61311 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143562 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143562 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204873 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204873 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204873 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204873 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2425671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2425671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9937173250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9937173250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12362844750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12362844750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12362844750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12362844750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168531 # number of writebacks +system.cpu.dcache.writebacks::total 168531 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28097 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28097 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136550 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136550 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 164647 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164647 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 164647 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164647 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61310 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61310 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 204870 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204870 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 204870 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204870 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2430963250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2430963250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9980296000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9980296000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12411259250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12411259250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12411259250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12411259250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses @@ -649,14 +665,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005859 system.cpu.dcache.demand_mshr_miss_rate::total 0.005859 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005859 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39563.398085 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39563.398085 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69218.687745 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69218.687745 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.354755 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39650.354755 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69520.033435 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69520.033435 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 31507e486..8732e3592 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022262 # Number of seconds simulated -sim_ticks 22262172500 # Number of ticks simulated -final_tick 22262172500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022330 # Number of seconds simulated +sim_ticks 22329989500 # Number of ticks simulated +final_tick 22329989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164105 # Simulator instruction rate (inst/s) -host_op_rate 164105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45900767 # Simulator tick rate (ticks/s) -host_mem_usage 245260 # Number of bytes of host memory used -host_seconds 485.01 # Real time elapsed on the host +host_inst_rate 232150 # Simulator instruction rate (inst/s) +host_op_rate 232150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65131135 # Simulator tick rate (ticks/s) +host_mem_usage 301288 # Number of bytes of host memory used +host_seconds 342.85 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10152448 # Number of bytes read from this memory -system.physmem.bytes_read::total 10639744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297472 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7614 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158632 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166246 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114023 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114023 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21888969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456040308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 477929277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21888969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21888969 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327796939 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327796939 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327796939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21888969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456040308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805726216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166246 # Number of read requests accepted -system.physmem.writeReqs 114023 # Number of write requests accepted -system.physmem.readBursts 166246 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114023 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10639232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7295808 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10639744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 487424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10151616 # Number of bytes read from this memory +system.physmem.bytes_read::total 10639040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296896 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296896 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158619 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166235 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114014 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114014 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21828223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454618037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 476446261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21828223 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21828223 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 326775613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 326775613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 326775613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21828223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454618037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 803221873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166235 # Number of read requests accepted +system.physmem.writeReqs 114014 # Number of write requests accepted +system.physmem.readBursts 166235 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114014 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10638592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10639040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10440 # Per bank write bursts -system.physmem.perBankRdBursts::1 10463 # Per bank write bursts -system.physmem.perBankRdBursts::2 10311 # Per bank write bursts -system.physmem.perBankRdBursts::3 10061 # Per bank write bursts -system.physmem.perBankRdBursts::4 10417 # Per bank write bursts -system.physmem.perBankRdBursts::5 10395 # Per bank write bursts -system.physmem.perBankRdBursts::6 9841 # Per bank write bursts -system.physmem.perBankRdBursts::7 10308 # Per bank write bursts -system.physmem.perBankRdBursts::8 10597 # Per bank write bursts -system.physmem.perBankRdBursts::9 10638 # Per bank write bursts +system.physmem.perBankRdBursts::0 10441 # Per bank write bursts +system.physmem.perBankRdBursts::1 10459 # Per bank write bursts +system.physmem.perBankRdBursts::2 10317 # Per bank write bursts +system.physmem.perBankRdBursts::3 10059 # Per bank write bursts +system.physmem.perBankRdBursts::4 10419 # Per bank write bursts +system.physmem.perBankRdBursts::5 10394 # Per bank write bursts +system.physmem.perBankRdBursts::6 9840 # Per bank write bursts +system.physmem.perBankRdBursts::7 10309 # Per bank write bursts +system.physmem.perBankRdBursts::8 10592 # Per bank write bursts +system.physmem.perBankRdBursts::9 10641 # Per bank write bursts system.physmem.perBankRdBursts::10 10546 # Per bank write bursts -system.physmem.perBankRdBursts::11 10227 # Per bank write bursts +system.physmem.perBankRdBursts::11 10221 # Per bank write bursts system.physmem.perBankRdBursts::12 10273 # Per bank write bursts -system.physmem.perBankRdBursts::13 10619 # Per bank write bursts -system.physmem.perBankRdBursts::14 10481 # Per bank write bursts -system.physmem.perBankRdBursts::15 10621 # Per bank write bursts +system.physmem.perBankRdBursts::13 10617 # Per bank write bursts +system.physmem.perBankRdBursts::14 10480 # Per bank write bursts +system.physmem.perBankRdBursts::15 10620 # Per bank write bursts system.physmem.perBankWrBursts::0 7082 # Per bank write bursts -system.physmem.perBankWrBursts::1 7258 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7170 # Per bank write bursts -system.physmem.perBankWrBursts::6 6776 # Per bank write bursts -system.physmem.perBankWrBursts::7 7085 # Per bank write bursts -system.physmem.perBankWrBursts::8 7222 # Per bank write bursts +system.physmem.perBankWrBursts::5 7168 # Per bank write bursts +system.physmem.perBankWrBursts::6 6771 # Per bank write bursts +system.physmem.perBankWrBursts::7 7079 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts system.physmem.perBankWrBursts::9 6942 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts -system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts system.physmem.perBankWrBursts::12 6966 # Per bank write bursts -system.physmem.perBankWrBursts::13 7288 # Per bank write bursts +system.physmem.perBankWrBursts::13 7287 # Per bank write bursts system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22262139000 # Total gap between requests +system.physmem.totGap 22329955500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166246 # Read request sizes (log2) +system.physmem.readPktSize::6 166235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114023 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 53911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15180 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114014 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15052 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,115 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52156 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.855817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.745106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.281593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18285 35.06% 35.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10756 20.62% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5580 10.70% 66.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3146 6.03% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2660 5.10% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1727 3.31% 80.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1787 3.43% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1244 2.39% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6971 13.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52156 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6968 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.856056 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.059287 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6967 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 51907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.459688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.593638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 345.239241 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18141 34.95% 34.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10684 20.58% 55.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5599 10.79% 66.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2999 5.78% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2733 5.27% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1724 3.32% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1780 3.43% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1211 2.33% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7036 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 51907 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.843208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.237754 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6969 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6968 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6968 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.360075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.330777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.045922 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6065 87.04% 87.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.42% 87.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 476 6.83% 94.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 227 3.26% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 92 1.32% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 39 0.56% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 17 0.24% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.16% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.11% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6968 # Writes before turning the bus around for reads -system.physmem.totQLat 5413019750 # Total ticks spent queuing -system.physmem.totMemAccLat 8529982250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831190000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32561.87 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.350882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.321302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.052955 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6113 87.69% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 29 0.42% 88.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 435 6.24% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 209 3.00% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 90 1.29% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 0.82% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.27% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 5 0.07% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.09% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads +system.physmem.totQLat 5659900500 # Total ticks spent queuing +system.physmem.totMemAccLat 8776675500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34049.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51311.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 477.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 477.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.80 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52799.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 476.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 326.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 476.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 326.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 146096 # Number of row buffer hits during reads -system.physmem.writeRowHits 81976 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.89 # Row buffer hit rate for writes -system.physmem.avgGap 79431.33 # Average gap between requests -system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 9551525000 # Time in different power states -system.physmem.memoryStateTime::REF 743340000 # Time in different power states +system.physmem.busUtil 6.27 # Data bus utilization in percentage +system.physmem.busUtilRead 3.72 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.55 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing +system.physmem.readRowHits 146045 # Number of row buffer hits during reads +system.physmem.writeRowHits 82245 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.14 # Row buffer hit rate for writes +system.physmem.avgGap 79678.98 # Average gap between requests +system.physmem.pageHitRate 81.46 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 9562649000 # Time in different power states +system.physmem.memoryStateTime::REF 745420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 11966317750 # Time in different power states +system.physmem.memoryStateTime::ACT 12015383500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 805726216 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35460 # Transaction distribution -system.membus.trans_dist::ReadResp 35460 # Transaction distribution -system.membus.trans_dist::Writeback 114023 # Transaction distribution -system.membus.trans_dist::ReadExReq 130786 # Transaction distribution -system.membus.trans_dist::ReadExResp 130786 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446515 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446515 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17937216 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17937216 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17937216 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1235956000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1525146000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 35446 # Transaction distribution +system.membus.trans_dist::ReadResp 35446 # Transaction distribution +system.membus.trans_dist::Writeback 114014 # Transaction distribution +system.membus.trans_dist::ReadExReq 130789 # Transaction distribution +system.membus.trans_dist::ReadExResp 130789 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446484 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17935936 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 280249 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 280249 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 280249 # Request fanout histogram +system.membus.reqLayer0.occupancy 1235861000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1525180500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16618538 # Number of BP lookups -system.cpu.branchPred.condPredicted 10751969 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 360716 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10752045 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7371197 # Number of BTB hits +system.cpu.branchPred.lookups 16618969 # Number of BP lookups +system.cpu.branchPred.condPredicted 10749423 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 361100 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10742405 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7368684 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.556233 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990414 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 68.594360 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1994688 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3025 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22632838 # DTB read hits -system.cpu.dtb.read_misses 226204 # DTB read misses -system.cpu.dtb.read_acv 19 # DTB read access violations -system.cpu.dtb.read_accesses 22859042 # DTB read accesses -system.cpu.dtb.write_hits 15863725 # DTB write hits -system.cpu.dtb.write_misses 44788 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15908513 # DTB write accesses -system.cpu.dtb.data_hits 38496563 # DTB hits -system.cpu.dtb.data_misses 270992 # DTB misses -system.cpu.dtb.data_acv 23 # DTB access violations -system.cpu.dtb.data_accesses 38767555 # DTB accesses -system.cpu.itb.fetch_hits 13910081 # ITB hits -system.cpu.itb.fetch_misses 31577 # ITB misses +system.cpu.dtb.read_hits 22640578 # DTB read hits +system.cpu.dtb.read_misses 225727 # DTB read misses +system.cpu.dtb.read_acv 15 # DTB read access violations +system.cpu.dtb.read_accesses 22866305 # DTB read accesses +system.cpu.dtb.write_hits 15860065 # DTB write hits +system.cpu.dtb.write_misses 44717 # DTB write misses +system.cpu.dtb.write_acv 7 # DTB write access violations +system.cpu.dtb.write_accesses 15904782 # DTB write accesses +system.cpu.dtb.data_hits 38500643 # DTB hits +system.cpu.dtb.data_misses 270444 # DTB misses +system.cpu.dtb.data_acv 22 # DTB access violations +system.cpu.dtb.data_accesses 38771087 # DTB accesses +system.cpu.itb.fetch_hits 13913295 # ITB hits +system.cpu.itb.fetch_misses 31383 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13941658 # ITB accesses +system.cpu.itb.fetch_accesses 13944678 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -315,141 +324,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44524349 # number of cpu cycles simulated +system.cpu.numCycles 44659983 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15777207 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106088567 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16618538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9361611 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27200271 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 960062 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 179 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5019 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 332851 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13910081 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206082 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15776454 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106093576 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16618969 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9363372 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27339445 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 961528 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 166 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5126 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 335016 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13913295 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207298 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43795615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.422356 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43937055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.414672 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.131710 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24068312 54.96% 54.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538186 3.51% 58.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1404705 3.21% 61.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1522843 3.48% 65.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4236021 9.67% 74.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1845751 4.21% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 684777 1.56% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069219 2.44% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7425801 16.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24208191 55.10% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1538198 3.50% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1405905 3.20% 61.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1524697 3.47% 65.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4231594 9.63% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1847884 4.21% 79.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 684699 1.56% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1071609 2.44% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7424278 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43795615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.373246 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.382709 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15090251 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9271065 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18462331 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 590423 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 381545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3739004 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100344 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103984343 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314766 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 381545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15473555 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6415386 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96680 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18647393 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2781056 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102842787 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3945 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 148156 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 330502 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2246834 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61884966 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124097859 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123771677 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 326181 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43937055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372122 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.375585 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15090542 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9411892 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18462094 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 590748 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 381779 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3738870 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100752 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103984898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 316746 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 381779 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15474298 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6446400 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97317 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18646914 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2890347 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102848317 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4603 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 150963 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 325598 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2361182 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61896036 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124089387 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123759844 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 329542 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9338085 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5827 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2465534 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23256981 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16451468 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1256796 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 554193 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91273922 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5644 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89085619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78698 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11197079 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4703509 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1061 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43795615 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.034122 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.247476 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9349155 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5813 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5869 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2465054 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23265818 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16448253 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1251433 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 545590 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91286622 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5695 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89090659 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79052 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11213817 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4716109 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1112 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43937055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.027688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246728 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17182377 39.23% 39.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5792116 13.23% 52.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5098261 11.64% 64.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4417263 10.09% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4344645 9.92% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649252 6.05% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1946446 4.44% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1380364 3.15% 97.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 984891 2.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17318675 39.42% 39.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5798510 13.20% 52.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5098508 11.60% 64.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4414835 10.05% 74.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4342383 9.88% 84.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2650303 6.03% 90.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1951252 4.44% 94.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1378643 3.14% 97.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 983946 2.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43795615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43937055 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 244209 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1174646 46.40% 56.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112477 43.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243742 9.63% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1177038 46.48% 56.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1111319 43.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49643458 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44096 0.05% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121526 0.14% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121394 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39070 0.04% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49642313 55.72% 55.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44169 0.05% 55.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122147 0.14% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121699 0.14% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39048 0.04% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued @@ -471,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23048961 25.87% 81.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16066967 18.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23057514 25.88% 81.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16063627 18.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89085619 # Type of FU issued -system.cpu.iq.rate 2.000829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2531332 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028415 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223962824 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102066580 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87151859 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 614059 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 431019 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 300727 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91309756 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307195 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1661224 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89090659 # Type of FU issued +system.cpu.iq.rate 1.994865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2532099 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028422 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224114042 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102090455 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87155295 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615482 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 436927 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 301089 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91314862 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307896 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1660010 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2980343 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6431 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21452 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1838091 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2989180 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6359 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21743 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1834876 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2952 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 325709 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2985 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 325715 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 381545 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1215876 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4878836 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100803158 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 157110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23256981 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16451468 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5576 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3364 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4856172 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21452 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 149650 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 157694 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 307344 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88311132 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22859779 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 774487 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 381779 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1212086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4898049 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100815278 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 146031 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23265818 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16448253 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5611 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3372 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4875472 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21743 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 149411 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 157245 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 306656 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88317091 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22866843 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 773568 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9523592 # number of nop insts executed -system.cpu.iew.exec_refs 38768607 # number of memory reference insts executed -system.cpu.iew.exec_branches 15170240 # Number of branches executed -system.cpu.iew.exec_stores 15908828 # Number of stores executed -system.cpu.iew.exec_rate 1.983435 # Inst execution rate -system.cpu.iew.wb_sent 87867079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87452586 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33893139 # num instructions producing a value -system.cpu.iew.wb_consumers 44339625 # num instructions consuming a value +system.cpu.iew.exec_nop 9522961 # number of nop insts executed +system.cpu.iew.exec_refs 38771937 # number of memory reference insts executed +system.cpu.iew.exec_branches 15172750 # Number of branches executed +system.cpu.iew.exec_stores 15905094 # Number of stores executed +system.cpu.iew.exec_rate 1.977544 # Inst execution rate +system.cpu.iew.wb_sent 87870804 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87456384 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33898733 # num instructions producing a value +system.cpu.iew.wb_consumers 44340261 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.964152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764398 # average fanout of values written-back +system.cpu.iew.wb_rate 1.958272 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764514 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9260506 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9275726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 262230 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42432313 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.081920 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.885099 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 262115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42571128 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.075131 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.882631 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20891279 49.23% 49.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6327574 14.91% 64.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2939948 6.93% 71.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1761291 4.15% 75.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1656008 3.90% 79.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1140180 2.69% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1204228 2.84% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795411 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5716394 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21025343 49.39% 49.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6328820 14.87% 64.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2946361 6.92% 71.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1760662 4.14% 75.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1654958 3.89% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1139679 2.68% 81.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1203795 2.83% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795933 1.87% 86.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5715577 13.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42432313 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42571128 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -594,229 +603,238 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5716394 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5715577 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132999755 # The number of ROB reads -system.cpu.rob.rob_writes 196569210 # The number of ROB writes -system.cpu.timesIdled 47704 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 728734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133154607 # The number of ROB reads +system.cpu.rob.rob_writes 196602232 # The number of ROB writes +system.cpu.timesIdled 47762 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 722928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559409 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559409 # CPI: Total CPI of All Threads -system.cpu.ipc 1.787601 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.787601 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116880103 # number of integer regfile reads -system.cpu.int_regfile_writes 57914968 # number of integer regfile writes -system.cpu.fp_regfile_reads 255764 # number of floating regfile reads -system.cpu.fp_regfile_writes 241194 # number of floating regfile writes -system.cpu.misc_regfile_reads 38207 # number of misc regfile reads +system.cpu.cpi 0.561113 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561113 # CPI: Total CPI of All Threads +system.cpu.ipc 1.782172 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.782172 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116877675 # number of integer regfile reads +system.cpu.int_regfile_writes 57921110 # number of integer regfile writes +system.cpu.fp_regfile_reads 255696 # number of floating regfile reads +system.cpu.fp_regfile_writes 241715 # number of floating regfile writes +system.cpu.misc_regfile_reads 38130 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1351038673 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 157664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157663 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143407 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191277 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579748 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 771025 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6120832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30077056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30077056 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 403861500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 157630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143405 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191099 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579901 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 771000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6115136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23962624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30077760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 469974 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 469974 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 469974 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403921992 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 144811965 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 321850746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 144682208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 321839246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 93590 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.549362 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13801419 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 95638 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 144.308946 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18781387250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.549362 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936792 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936792 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 93501 # number of replacements +system.cpu.icache.tags.tagsinuse 1918.858110 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13804656 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 95549 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 144.477242 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18832337250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.858110 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936942 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1479 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1480 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 377 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27915798 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27915798 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13801419 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13801419 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13801419 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13801419 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13801419 # number of overall hits -system.cpu.icache.overall_hits::total 13801419 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 108661 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 108661 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 108661 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 108661 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 108661 # number of overall misses -system.cpu.icache.overall_misses::total 108661 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2007129462 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2007129462 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2007129462 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2007129462 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2007129462 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2007129462 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13910080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13910080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13910080 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13910080 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13910080 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13910080 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007812 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007812 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007812 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007812 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007812 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007812 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18471.479758 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18471.479758 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18471.479758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18471.479758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18471.479758 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 421 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27922137 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27922137 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13804656 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13804656 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13804656 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13804656 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13804656 # number of overall hits +system.cpu.icache.overall_hits::total 13804656 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 108638 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 108638 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 108638 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 108638 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 108638 # number of overall misses +system.cpu.icache.overall_misses::total 108638 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2007932205 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2007932205 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2007932205 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2007932205 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2007932205 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2007932205 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13913294 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13913294 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13913294 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13913294 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13913294 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13913294 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007808 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007808 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007808 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007808 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007808 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007808 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18482.779552 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18482.779552 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18482.779552 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18482.779552 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18482.779552 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18482.779552 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 52.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13022 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 13022 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 13022 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 13022 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 13022 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 13022 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95639 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 95639 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 95639 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 95639 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 95639 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 95639 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1547349535 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1547349535 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1547349535 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1547349535 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1547349535 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1547349535 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006876 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006876 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006876 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006876 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006876 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006876 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16179.064346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16179.064346 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16179.064346 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16179.064346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16179.064346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16179.064346 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13088 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 13088 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 13088 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 13088 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 13088 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 13088 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95550 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 95550 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 95550 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 95550 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 95550 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 95550 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1542742292 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1542742292 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1542742292 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1542742292 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1542742292 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1542742292 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006868 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006868 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006868 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006868 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006868 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006868 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16145.916190 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16145.916190 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16145.916190 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16145.916190 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16145.916190 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16145.916190 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132342 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30650.396196 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 161877 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164409 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.984599 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132334 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30651.520219 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 161905 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164393 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.984866 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26717.381554 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2107.778355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1825.236287 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815350 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064324 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.055702 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.935376 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32067 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3055 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 82610.959217 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78150.365193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89403.543111 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89403.543111 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61852.829198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88211.771572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87003.994291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61852.829198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88211.771572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87003.994291 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201336 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.830097 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34080339 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205432 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.895961 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 201389 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.903515 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34089462 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205485 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.897569 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.830097 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4071.903515 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994117 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994117 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2800 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1220 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2789 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1230 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71000880 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71000880 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20516147 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20516147 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13564136 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13564136 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34080283 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34080283 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34080283 # number of overall hits -system.cpu.dcache.overall_hits::total 34080283 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268143 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268143 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1049241 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1049241 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 71018847 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71018847 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20525187 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20525187 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13564218 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13564218 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34089405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34089405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34089405 # number of overall hits +system.cpu.dcache.overall_hits::total 34089405 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 268059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 268059 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1049159 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1049159 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1317384 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1317384 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1317384 # number of overall misses -system.cpu.dcache.overall_misses::total 1317384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16930688495 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16930688495 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85479699625 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85479699625 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102410388120 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102410388120 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102410388120 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102410388120 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20784290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20784290 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1317218 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1317218 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1317218 # number of overall misses +system.cpu.dcache.overall_misses::total 1317218 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17086669746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17086669746 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 86915323054 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 86915323054 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104001992800 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104001992800 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104001992800 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104001992800 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20793246 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20793246 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35397667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35397667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35397667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35397667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012901 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012901 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071800 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071800 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017544 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017544 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037217 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037217 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037217 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037217 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63140.520152 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63140.520152 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81468.127556 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81468.127556 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77737.689330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77737.689330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77737.689330 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6284356 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35406623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35406623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35406623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35406623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012892 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012892 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071794 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071794 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017241 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017241 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037203 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63742.197598 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63742.197598 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82842.851326 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82842.851326 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78955.793802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78955.793802 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6406656 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146253 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 146327 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.969074 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.783143 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168884 # number of writebacks -system.cpu.dcache.writebacks::total 168884 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206118 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905835 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 905835 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1111953 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1111953 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1111953 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1111953 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62025 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62025 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168931 # number of writebacks +system.cpu.dcache.writebacks::total 168931 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205979 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205979 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905755 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 905755 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1111734 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1111734 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1111734 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1111734 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62080 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62080 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143404 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143404 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205431 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205431 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205431 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205431 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3026595754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3026595754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13337681700 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13337681700 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16364277454 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16364277454 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16364277454 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16364277454 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 205484 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205484 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205484 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205484 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3049561754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3049561754 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13566762195 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13566762195 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16616323949 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16616323949 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16616323949 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16616323949 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002986 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002986 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017544 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017544 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017241 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017241 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005804 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005804 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48796.384587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48796.384587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93006.441153 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93006.441153 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79658.267029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79658.267029 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49123.095264 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49123.095264 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94605.186710 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94605.186710 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index c4c8f0d89..db2ebe7dc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3162077 # Simulator instruction rate (inst/s) -host_op_rate 3162075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1582850501 # Simulator tick rate (ticks/s) -host_mem_usage 263736 # Number of bytes of host memory used -host_seconds 27.94 # Real time elapsed on the host +host_inst_rate 2813944 # Simulator instruction rate (inst/s) +host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1408584494 # Simulator tick rate (ticks/s) +host_mem_usage 287952 # Number of bytes of host memory used +host_seconds 31.39 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 2072610067 # Wr system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12937468537 # Throughput (bytes/s) -system.membus.data_through_bus 572107835 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 108714711 # Transaction distribution +system.membus.trans_dist::ReadResp 108714711 # Transaction distribution +system.membus.trans_dist::WriteReq 14613377 # Transaction distribution +system.membus.trans_dist::WriteResp 14613377 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 123328088 # Request fanout histogram +system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram +system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 123328088 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index beac32b45..06edb9753 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1560477 # Simulator instruction rate (inst/s) -host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2360564466 # Simulator tick rate (ticks/s) -host_mem_usage 272464 # Number of bytes of host memory used -host_seconds 56.61 # Real time elapsed on the host +host_inst_rate 1471745 # Simulator instruction rate (inst/s) +host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2226337698 # Simulator tick rate (ticks/s) +host_mem_usage 297712 # Number of bytes of host memory used +host_seconds 60.02 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 54587966 # To system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 133682617 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34272 # Transaction distribution system.membus.trans_dist::ReadResp 34272 # Transaction distribution system.membus.trans_dist::Writeback 113982 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 130881 # Tr system.membus.trans_dist::ReadExResp 130881 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17864640 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 279135 # Request fanout histogram system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) @@ -484,7 +492,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution @@ -493,11 +500,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) |