diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/50.vortex/ref/arm/linux/minor-timing | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/minor-timing')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 940 |
1 files changed, 469 insertions, 471 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index a19ba8014..c63d403d5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064367 # Number of seconds simulated -sim_ticks 64366581500 # Number of ticks simulated -final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056337 # Number of seconds simulated +sim_ticks 56337328500 # Number of ticks simulated +final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99170 # Simulator instruction rate (inst/s) -host_op_rate 140730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90012135 # Simulator tick rate (ticks/s) -host_mem_usage 295432 # Number of bytes of host memory used -host_seconds 715.09 # Real time elapsed on the host +host_inst_rate 184341 # Simulator instruction rate (inst/s) +host_op_rate 235745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 146446418 # Simulator tick rate (ticks/s) +host_mem_usage 326872 # Number of bytes of host memory used +host_seconds 384.70 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated -sim_ops 100634375 # Number of ops (including micro ops) simulated +sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory -system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory -system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 129052 # Number of read requests accepted -system.physmem.writeReqs 83957 # Number of write requests accepted -system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 8247168 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 323904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 323904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 128862 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128862 # Number of read requests accepted +system.physmem.writeReqs 83951 # Number of write requests accepted +system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8196 # Per bank write bursts -system.physmem.perBankRdBursts::1 8381 # Per bank write bursts -system.physmem.perBankRdBursts::2 8249 # Per bank write bursts -system.physmem.perBankRdBursts::3 8185 # Per bank write bursts -system.physmem.perBankRdBursts::4 8327 # Per bank write bursts -system.physmem.perBankRdBursts::5 8459 # Per bank write bursts -system.physmem.perBankRdBursts::6 8094 # Per bank write bursts -system.physmem.perBankRdBursts::7 7981 # Per bank write bursts -system.physmem.perBankRdBursts::8 8076 # Per bank write bursts -system.physmem.perBankRdBursts::9 7644 # Per bank write bursts -system.physmem.perBankRdBursts::10 7831 # Per bank write bursts -system.physmem.perBankRdBursts::11 7843 # Per bank write bursts -system.physmem.perBankRdBursts::12 7891 # Per bank write bursts -system.physmem.perBankRdBursts::13 7884 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8027 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts -system.physmem.perBankWrBursts::1 5375 # Per bank write bursts -system.physmem.perBankWrBursts::2 5284 # Per bank write bursts +system.physmem.perBankRdBursts::0 8164 # Per bank write bursts +system.physmem.perBankRdBursts::1 8373 # Per bank write bursts +system.physmem.perBankRdBursts::2 8238 # Per bank write bursts +system.physmem.perBankRdBursts::3 8169 # Per bank write bursts +system.physmem.perBankRdBursts::4 8316 # Per bank write bursts +system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::7 7969 # Per bank write bursts +system.physmem.perBankRdBursts::8 8071 # Per bank write bursts +system.physmem.perBankRdBursts::9 7635 # Per bank write bursts +system.physmem.perBankRdBursts::10 7816 # Per bank write bursts +system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7876 # Per bank write bursts +system.physmem.perBankRdBursts::14 7976 # Per bank write bursts +system.physmem.perBankRdBursts::15 8004 # Per bank write bursts +system.physmem.perBankWrBursts::0 5182 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5201 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5034 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5146 # Per bank write bursts -system.physmem.perBankWrBursts::12 5344 # Per bank write bursts +system.physmem.perBankWrBursts::6 5198 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5033 # Per bank write bursts +system.physmem.perBankWrBursts::9 5086 # Per bank write bursts +system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::11 5143 # Per bank write bursts +system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5227 # Per bank write bursts +system.physmem.perBankWrBursts::15 5224 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64366550000 # Total gap between requests +system.physmem.totGap 56337297000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 129052 # Read request sizes (log2) +system.physmem.readPktSize::6 128862 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83957 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83951 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,25 +140,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -189,96 +189,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.918314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.655421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2767 7.13% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2567 6.61% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1675 4.31% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1312 3.38% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1197 3.08% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4479 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads -system.physmem.totQLat 1458157250 # Total ticks spent queuing -system.physmem.totMemAccLat 3877751000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11299.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1494390000 # Total ticks spent queuing +system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30049.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.65 # Data bus utilization in percentage -system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.89 # Data bus utilization in percentage +system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing -system.physmem.readRowHits 112129 # Number of row buffer hits during reads -system.physmem.writeRowHits 62016 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes -system.physmem.avgGap 302177.61 # Average gap between requests -system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 37447706500 # Time in different power states -system.physmem.memoryStateTime::REF 2149160000 # Time in different power states +system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing +system.physmem.readRowHits 112251 # Number of row buffer hits during reads +system.physmem.writeRowHits 62167 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes +system.physmem.avgGap 264726.76 # Average gap between requests +system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states +system.physmem.memoryStateTime::REF 1881100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24764549750 # Time in different power states +system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 211795868 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26785 # Transaction distribution -system.membus.trans_dist::ReadResp 26785 # Transaction distribution -system.membus.trans_dist::Writeback 83957 # Transaction distribution -system.membus.trans_dist::ReadExReq 102267 # Transaction distribution -system.membus.trans_dist::ReadExResp 102267 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13632576 # Total data (bytes) +system.membus.throughput 241758570 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26583 # Transaction distribution +system.membus.trans_dist::ReadResp 26583 # Transaction distribution +system.membus.trans_dist::Writeback 83951 # Transaction distribution +system.membus.trans_dist::ReadExReq 102279 # Transaction distribution +system.membus.trans_dist::ReadExResp 102279 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13620032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 975516500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1243562250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16883830 # Number of BP lookups -system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits +system.cpu.branchPred.lookups 14808792 # Number of BP lookups +system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -364,70 +362,70 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 128733163 # number of cpu cycles simulated +system.cpu.numCycles 112674657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed -system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2952341 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.815313 # CPI: cycles per instruction -system.cpu.ipc 0.550869 # IPC: instructions per cycle -system.cpu.tickCycles 109168240 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19564923 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 43522 # number of replacements -system.cpu.icache.tags.tagsinuse 1864.297124 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. +system.cpu.cpi 1.588866 # CPI: cycles per instruction +system.cpu.ipc 0.629380 # IPC: instructions per cycle +system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 42434 # number of replacements +system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297124 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses -system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits -system.cpu.icache.overall_hits::total 27427302 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses -system.cpu.icache.overall_misses::total 45565 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 909865240 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 909865240 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 909865240 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 909865240 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 909865240 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 909865240 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19968.511796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19968.511796 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits +system.cpu.icache.overall_hits::total 24948252 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses +system.cpu.icache.overall_misses::total 44477 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,123 +434,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816831760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 816831760 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816831760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 816831760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816831760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 816831760 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44477 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44477 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44477 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) +system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 269478689 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 95911 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30027.975303 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 95725 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.834967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits -system.cpu.l2cache.overall_hits::total 77402 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses -system.cpu.l2cache.overall_misses::total 129124 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992283500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1992283500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436939000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7436939000 # 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miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # 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number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits -system.cpu.dcache.overall_hits::total 47220249 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses -system.cpu.dcache.overall_misses::total 264397 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169299439 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2169299439 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315314750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15315314750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17484614189 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17484614189 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17484614189 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17484614189 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66130.153478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66130.153478 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,48 +680,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks -system.cpu.dcache.writebacks::total 128565 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001760311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001760311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593417311 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9593417311 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593417311 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9593417311 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128423 # number of writebacks +system.cpu.dcache.writebacks::total 128423 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |