diff options
| author | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2015-03-19 08:41:32 -0400 |
| commit | 1483496803f8a8618f62adc5439ce435359b36fe (patch) | |
| tree | a6134ff85d7e6e07e6d34293513f91b16ff94515 /tests/long/se/50.vortex/ref/arm/linux/minor-timing | |
| parent | f1c3fda965dd4b28ab6b2e99f5f3210fa2089a17 (diff) | |
| download | gem5-1483496803f8a8618f62adc5439ce435359b36fe.tar.xz | |
stats: update Minor stats due to PF bug fix
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads. Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly. These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/minor-timing')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini | 30 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr | 1 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout | 14 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 1031 |
4 files changed, 553 insertions, 523 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index fd6ea1264..97bcd61c2 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -132,6 +133,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -166,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -183,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -591,6 +593,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -651,6 +654,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -658,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -675,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -733,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -749,14 +757,16 @@ eventq_index=0 type=LiveProcess cmd=vortex lendian.raw cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -786,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -821,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -830,6 +843,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr index 1a4f96712..341b479f7 100644..100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr @@ -1 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout index 0b495a4c8..0ebe6ca65 100644..100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 17:09:29 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0xcee8df0 + 0: system.cpu.isa: ISA system set to: 0 0x3b079b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 64581408500 because target called exit() +Exiting @ tick 57738195500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 20f3ef2c3..6d11e3682 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058730 # Number of seconds simulated -sim_ticks 58730125500 # Number of ticks simulated -final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057738 # Number of seconds simulated +sim_ticks 57738195500 # Number of ticks simulated +final_tick 57738195500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197162 # Simulator instruction rate (inst/s) -host_op_rate 252141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163284235 # Simulator tick rate (ticks/s) -host_mem_usage 321164 # Number of bytes of host memory used -host_seconds 359.68 # Real time elapsed on the host +host_inst_rate 113055 # Simulator instruction rate (inst/s) +host_op_rate 144580 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92047581 # Simulator tick rate (ticks/s) +host_mem_usage 250264 # Number of bytes of host memory used +host_seconds 627.26 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7922944 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128871 # Number of read requests accepted -system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 123796 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5617633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 137221885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 142839518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5617633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5617633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 93057844 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 93057844 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 93057844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5617633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 137221885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 235897362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128864 # Number of read requests accepted +system.physmem.writeReqs 83953 # Number of write requests accepted +system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8376 # Per bank write bursts -system.physmem.perBankRdBursts::2 8228 # Per bank write bursts -system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8319 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7969 # Per bank write bursts -system.physmem.perBankRdBursts::8 8071 # Per bank write bursts -system.physmem.perBankRdBursts::9 7640 # Per bank write bursts -system.physmem.perBankRdBursts::10 7818 # Per bank write bursts -system.physmem.perBankRdBursts::11 7832 # Per bank write bursts -system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7879 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8007 # Per bank write bursts -system.physmem.perBankWrBursts::0 5180 # Per bank write bursts +system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::1 8374 # Per bank write bursts +system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::3 8170 # Per bank write bursts +system.physmem.perBankRdBursts::4 8316 # Per bank write bursts +system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::7 7971 # Per bank write bursts +system.physmem.perBankRdBursts::8 8070 # Per bank write bursts +system.physmem.perBankRdBursts::9 7642 # Per bank write bursts +system.physmem.perBankRdBursts::10 7819 # Per bank write bursts +system.physmem.perBankRdBursts::11 7829 # Per bank write bursts +system.physmem.perBankRdBursts::12 7880 # Per bank write bursts +system.physmem.perBankRdBursts::13 7877 # Per bank write bursts +system.physmem.perBankRdBursts::14 7978 # Per bank write bursts +system.physmem.perBankRdBursts::15 8008 # Per bank write bursts +system.physmem.perBankWrBursts::0 5182 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts system.physmem.perBankWrBursts::6 5197 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::7 5047 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::9 5088 # Per bank write bursts system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5227 # Per bank write bursts +system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58730091000 # Total gap between requests +system.physmem.totGap 57738161000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128871 # Read request sizes (log2) +system.physmem.readPktSize::6 128864 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83951 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83953 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12131 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,98 +193,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.991784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.320111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.607526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12100 31.46% 31.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8198 21.31% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4148 10.78% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2890 7.51% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2484 6.46% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1581 4.11% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1319 3.43% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1187 3.09% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4555 11.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38462 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.974593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.421207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads -system.physmem.totQLat 1533027250 # Total ticks spent queuing -system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.276571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.259351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.782645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4530 87.86% 87.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.17% 88.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 479 9.29% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 112 2.17% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 15 0.29% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8 0.16% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads +system.physmem.totQLat 1653247250 # Total ticks spent queuing +system.physmem.totMemAccLat 4069353500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12829.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31579.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 142.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 93.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 142.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 93.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.81 # Data bus utilization in percentage -system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 112070 # Number of row buffer hits during reads -system.physmem.writeRowHits 62147 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes -system.physmem.avgGap 275958.74 # Average gap between requests -system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.329716 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states +system.physmem.busUtil 1.84 # Data bus utilization in percentage +system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing +system.physmem.readRowHits 112168 # Number of row buffer hits during reads +system.physmem.writeRowHits 62144 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.02 # Row buffer hit rate for writes +system.physmem.avgGap 271304.27 # Average gap between requests +system.physmem.pageHitRate 81.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 151283160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82545375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512694000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272322000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11678597190 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24396798750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40865212875 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.802856 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40459125250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1927900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15348292250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.358131 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states +system.physmem_1.actEnergy 139489560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76110375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492070800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271492560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11151778680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24858920250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40760834625 # Total energy per rank (pJ) +system.physmem_1.averagePower 705.994980 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41228847750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1927900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14578569750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14827059 # Number of BP lookups -system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits +system.cpu.branchPred.lookups 14838314 # Number of BP lookups +system.cpu.branchPred.condPredicted 9926302 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397118 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9672403 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6752101 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 69.807896 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1719649 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,89 +405,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 117460251 # number of cpu cycles simulated +system.cpu.numCycles 115476391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1150638 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.656350 # CPI: cycles per instruction -system.cpu.ipc 0.603737 # IPC: instructions per cycle -system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked -system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156434 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy +system.cpu.cpi 1.628375 # CPI: cycles per instruction +system.cpu.ipc 0.614109 # IPC: instructions per cycle +system.cpu.tickCycles 96920862 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18555529 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156418 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.282815 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42627759 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160514 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.570349 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 830513250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.282815 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86021754 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86021754 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22869180 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22869180 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84553 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84553 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits -system.cpu.dcache.overall_hits::total 42634623 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses -system.cpu.dcache.overall_misses::total 262226 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42511368 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42511368 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42595921 # number of overall hits +system.cpu.dcache.overall_hits::total 42595921 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 43659 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 43659 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 302861 # number of overall misses +system.cpu.dcache.overall_misses::total 302861 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1477411436 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1477411436 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16920342250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16920342250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18397753686 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18397753686 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18397753686 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18397753686 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22920669 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22920669 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128212 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128212 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42770570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42770570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42898782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42898782 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002246 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002246 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340522 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.340522 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28693.729457 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28693.729457 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81460.198688 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81460.198688 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70978.440313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70978.440313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60746.526248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60746.526248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,102 +504,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks -system.cpu.dcache.writebacks::total 128445 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128435 # number of writebacks +system.cpu.dcache.writebacks::total 128435 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21989 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21989 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100683 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29500 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29500 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23984 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23984 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160514 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160514 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558489314 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 558489314 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444692500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444692500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1685620500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1685620500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9003181814 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9003181814 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10688802314 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10688802314 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187065 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187065 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18931.841153 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18931.841153 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78900.238251 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78900.238251 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70281.041528 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70281.041528 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65942.882985 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65942.882985 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66591.090584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66591.090584 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42774 # number of replacements -system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42756 # number of replacements +system.cpu.icache.tags.tagsinuse 1854.448619 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25096729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44798 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 560.219854 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1854.448619 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.905492 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.905492 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits -system.cpu.icache.overall_hits::total 25093452 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses -system.cpu.icache.overall_misses::total 44817 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001783 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50327854 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50327854 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25096729 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25096729 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25096729 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25096729 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25096729 # number of overall hits +system.cpu.icache.overall_hits::total 25096729 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44799 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44799 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44799 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44799 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44799 # number of overall misses +system.cpu.icache.overall_misses::total 44799 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 934736739 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 934736739 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 934736739 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 934736739 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 934736739 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 934736739 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25141528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25141528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25141528 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20865.125092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20865.125092 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,123 +616,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -724,116 +741,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks -system.cpu.l2cache.writebacks::total 83951 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83953 # number of writebacks +system.cpu.l2cache.writebacks::total 83953 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5069 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21514 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26583 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 5069 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128872 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123796 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5069 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128872 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342505250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1501079000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1843584250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6966637250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6966637250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342505250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8467716250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8810221500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342505250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8467716250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8810221500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402329 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270483 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627582 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627582 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67568.603275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69743.019096 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69328.529257 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68113.387270 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68113.387270 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 123796 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339459750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1581559750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1921019500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7009102000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7009102000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339459750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8590661750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8930121500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339459750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8590661750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8930121500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270474 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627651 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66967.794437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73513.049642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72264.962570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68527.228642 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68527.228642 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98313 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98312 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89597 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2867072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21359808 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333748 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 333748 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333748 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295309000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68157239 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268247686 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26591 # Transaction distribution -system.membus.trans_dist::ReadResp 26591 # Transaction distribution -system.membus.trans_dist::Writeback 83951 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 26582 # Transaction distribution +system.membus.trans_dist::ReadResp 26582 # Transaction distribution +system.membus.trans_dist::Writeback 83953 # Transaction distribution +system.membus.trans_dist::ReadExReq 102282 # Transaction distribution +system.membus.trans_dist::ReadExResp 102282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341681 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212822 # Request fanout histogram +system.membus.snoop_fanout::samples 212817 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212817 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212822 # Request fanout histogram -system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212817 # Request fanout histogram +system.membus.reqLayer0.occupancy 578407500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 680129500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |