diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/50.vortex/ref/arm/linux/minor-timing | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/minor-timing')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 976 |
1 files changed, 486 insertions, 490 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index b9814d1e2..20f3ef2c3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057816 # Number of seconds simulated -sim_ticks 57815555000 # Number of ticks simulated -final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058730 # Number of seconds simulated +sim_ticks 58730125500 # Number of ticks simulated +final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131971 # Simulator instruction rate (inst/s) -host_op_rate 168772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107593052 # Simulator tick rate (ticks/s) -host_mem_usage 309228 # Number of bytes of host memory used -host_seconds 537.35 # Real time elapsed on the host +host_inst_rate 197162 # Simulator instruction rate (inst/s) +host_op_rate 252141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163284235 # Simulator tick rate (ticks/s) +host_mem_usage 321164 # Number of bytes of host memory used +host_seconds 359.68 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128872 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128871 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8375 # Per bank write bursts -system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::1 8376 # Per bank write bursts +system.physmem.perBankRdBursts::2 8228 # Per bank write bursts system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8320 # Per bank write bursts +system.physmem.perBankRdBursts::4 8319 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7970 # Per bank write bursts +system.physmem.perBankRdBursts::7 7969 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts system.physmem.perBankRdBursts::9 7640 # Per bank write bursts -system.physmem.perBankRdBursts::10 7820 # Per bank write bursts -system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::10 7818 # Per bank write bursts +system.physmem.perBankRdBursts::11 7832 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5183 # Per bank write bursts +system.physmem.perBankRdBursts::15 8007 # Per bank write bursts +system.physmem.perBankWrBursts::0 5180 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5194 # Per bank write bursts -system.physmem.perBankWrBursts::7 5048 # Per bank write bursts +system.physmem.perBankWrBursts::6 5197 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5086 # Per bank write bursts -system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5225 # Per bank write bursts +system.physmem.perBankWrBursts::15 5227 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57815523000 # Total gap between requests +system.physmem.totGap 58730091000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128872 # Read request sizes (log2) +system.physmem.readPktSize::6 128871 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83951 # Write request sizes (log2) system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,100 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 1505377000 # Total ticks spent queuing -system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads +system.physmem.totQLat 1533027250 # Total ticks spent queuing +system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.84 # Data bus utilization in percentage -system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.81 # Data bus utilization in percentage +system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing -system.physmem.readRowHits 112203 # Number of row buffer hits during reads -system.physmem.writeRowHits 62134 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes -system.physmem.avgGap 271660.13 # Average gap between requests -system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.837327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 112070 # Number of row buffer hits during reads +system.physmem.writeRowHits 62147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes +system.physmem.avgGap 275958.74 # Average gap between requests +system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.329716 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.292941 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.358131 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14822198 # Number of BP lookups -system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits +system.cpu.branchPred.lookups 14827059 # Number of BP lookups +system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -406,89 +404,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115631110 # number of cpu cycles simulated +system.cpu.numCycles 117460251 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.630556 # CPI: cycles per instruction -system.cpu.ipc 0.613288 # IPC: instructions per cycle -system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156428 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy +system.cpu.cpi 1.656350 # CPI: cycles per instruction +system.cpu.ipc 0.603737 # IPC: instructions per cycle +system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked +system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156434 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits -system.cpu.dcache.overall_hits::total 42633064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses -system.cpu.dcache.overall_misses::total 262131 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits +system.cpu.dcache.overall_hits::total 42634623 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses +system.cpu.dcache.overall_misses::total 262226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,32 +495,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks -system.cpu.dcache.writebacks::total 128441 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks +system.cpu.dcache.writebacks::total 128445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -531,68 +529,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # 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Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 803 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits -system.cpu.icache.overall_hits::total 25083355 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44725 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44725 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44725 # number of overall misses -system.cpu.icache.overall_misses::total 44725 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 895927489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 895927489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 895927489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 895927489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 895927489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 895927489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25128080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25128080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25128080 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25128080 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25128080 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25128080 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20031.917026 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20031.917026 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits +system.cpu.icache.overall_hits::total 25093452 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses +system.cpu.icache.overall_misses::total 44817 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001783 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001783 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001783 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,123 +599,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44725 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44725 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44725 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44725 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44725 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44725 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804564511 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 804564511 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804564511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 804564511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44817 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44817 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44817 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 868759010 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 868759010 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 868759010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 868759010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 868759010 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 868759010 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001783 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001783 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19384.586429 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19384.586429 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95733 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29936.958460 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99697 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126852 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 29885.598621 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99802 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126851 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.786766 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 39644 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31904 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4755 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39644 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627582 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627582 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67568.603275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69743.019096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69328.529257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68113.387270 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68113.387270 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128441 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107036 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98312 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadReq 26591 # Transaction distribution system.membus.trans_dist::ReadResp 26591 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212823 # Request fanout histogram +system.membus.snoop_fanout::samples 212822 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212823 # Request fanout histogram -system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.snoop_fanout::total 212822 # Request fanout histogram +system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |