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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
| commit | 9954eb74df98c4749651eb78098595f78d642105 (patch) | |
| tree | 74766341f05f999e2ad00626284e09dc6d0a2c58 /tests/long/se/50.vortex/ref/arm/linux/minor-timing | |
| parent | 67925a833445a8b2ddce0fae4c86677ce0f4298d (diff) | |
| download | gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz | |
stats: update stale config.ini files, eio and few other stats.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/minor-timing')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index 97bcd61c2..5bde02f67 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -125,7 +125,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -137,7 +136,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -148,7 +147,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -597,7 +595,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -608,7 +606,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -708,7 +705,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -719,7 +716,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] |