diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1662 |
1 files changed, 830 insertions, 832 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 4fc60452d..6b580b547 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033346 # Number of seconds simulated -sim_ticks 33346420000 # Number of ticks simulated -final_tick 33346420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033788 # Number of seconds simulated +sim_ticks 33787619000 # Number of ticks simulated +final_tick 33787619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116263 # Simulator instruction rate (inst/s) -host_op_rate 148687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54676178 # Simulator tick rate (ticks/s) -host_mem_usage 326572 # Number of bytes of host memory used -host_seconds 609.89 # Real time elapsed on the host +host_inst_rate 117892 # Simulator instruction rate (inst/s) +host_op_rate 150770 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56175899 # Simulator tick rate (ticks/s) +host_mem_usage 326928 # Number of bytes of host memory used +host_seconds 601.46 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 581760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2519040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6191552 # Number of bytes read from this memory -system.physmem.bytes_read::total 9292352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 581760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 581760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6257152 # Number of bytes written to this memory -system.physmem.bytes_written::total 6257152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96743 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145193 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97768 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97768 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17445951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75541542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 185673665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 278661158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17445951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17445951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187640892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187640892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187640892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17445951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75541542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 185673665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 466302050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145193 # Number of read requests accepted -system.physmem.writeReqs 97768 # Number of write requests accepted -system.physmem.readBursts 145193 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97768 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9285376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 6255360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9292352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6257152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9137 # Per bank write bursts -system.physmem.perBankRdBursts::1 9395 # Per bank write bursts -system.physmem.perBankRdBursts::2 9161 # Per bank write bursts -system.physmem.perBankRdBursts::3 9548 # Per bank write bursts -system.physmem.perBankRdBursts::4 9715 # Per bank write bursts -system.physmem.perBankRdBursts::5 9765 # Per bank write bursts -system.physmem.perBankRdBursts::6 9098 # Per bank write bursts -system.physmem.perBankRdBursts::7 9032 # Per bank write bursts -system.physmem.perBankRdBursts::8 9205 # Per bank write bursts -system.physmem.perBankRdBursts::9 8593 # Per bank write bursts -system.physmem.perBankRdBursts::10 8826 # Per bank write bursts -system.physmem.perBankRdBursts::11 8653 # Per bank write bursts -system.physmem.perBankRdBursts::12 8623 # Per bank write bursts -system.physmem.perBankRdBursts::13 8667 # Per bank write bursts -system.physmem.perBankRdBursts::14 8699 # Per bank write bursts -system.physmem.perBankRdBursts::15 8967 # Per bank write bursts -system.physmem.perBankWrBursts::0 5976 # Per bank write bursts -system.physmem.perBankWrBursts::1 6230 # Per bank write bursts -system.physmem.perBankWrBursts::2 6094 # Per bank write bursts -system.physmem.perBankWrBursts::3 6205 # Per bank write bursts -system.physmem.perBankWrBursts::4 6124 # Per bank write bursts -system.physmem.perBankWrBursts::5 6340 # Per bank write bursts -system.physmem.perBankWrBursts::6 6054 # Per bank write bursts -system.physmem.perBankWrBursts::7 6041 # Per bank write bursts -system.physmem.perBankWrBursts::8 6001 # Per bank write bursts -system.physmem.perBankWrBursts::9 6103 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 736896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2854400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6176576 # Number of bytes read from this memory +system.physmem.bytes_read::total 9767872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 736896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 736896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6229632 # Number of bytes written to this memory +system.physmem.bytes_written::total 6229632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 11514 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96509 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152623 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97338 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97338 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21809646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 84480650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 182805897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 289096192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21809646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21809646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184376176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184376176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184376176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21809646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 84480650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 182805897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 473472369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 152624 # Number of read requests accepted +system.physmem.writeReqs 97338 # Number of write requests accepted +system.physmem.readBursts 152624 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97338 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9758080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6227712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9767936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6229632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 27837 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9027 # Per bank write bursts +system.physmem.perBankRdBursts::1 9355 # Per bank write bursts +system.physmem.perBankRdBursts::2 9548 # Per bank write bursts +system.physmem.perBankRdBursts::3 12185 # Per bank write bursts +system.physmem.perBankRdBursts::4 10599 # Per bank write bursts +system.physmem.perBankRdBursts::5 10432 # Per bank write bursts +system.physmem.perBankRdBursts::6 9787 # Per bank write bursts +system.physmem.perBankRdBursts::7 9285 # Per bank write bursts +system.physmem.perBankRdBursts::8 9499 # Per bank write bursts +system.physmem.perBankRdBursts::9 9569 # Per bank write bursts +system.physmem.perBankRdBursts::10 9134 # Per bank write bursts +system.physmem.perBankRdBursts::11 8776 # Per bank write bursts +system.physmem.perBankRdBursts::12 8706 # Per bank write bursts +system.physmem.perBankRdBursts::13 8772 # Per bank write bursts +system.physmem.perBankRdBursts::14 8686 # Per bank write bursts +system.physmem.perBankRdBursts::15 9110 # Per bank write bursts +system.physmem.perBankWrBursts::0 5979 # Per bank write bursts +system.physmem.perBankWrBursts::1 6226 # Per bank write bursts +system.physmem.perBankWrBursts::2 6146 # Per bank write bursts +system.physmem.perBankWrBursts::3 6158 # Per bank write bursts +system.physmem.perBankWrBursts::4 6081 # Per bank write bursts +system.physmem.perBankWrBursts::5 6325 # Per bank write bursts +system.physmem.perBankWrBursts::6 6021 # Per bank write bursts +system.physmem.perBankWrBursts::7 5966 # Per bank write bursts +system.physmem.perBankWrBursts::8 5954 # Per bank write bursts +system.physmem.perBankWrBursts::9 6102 # Per bank write bursts system.physmem.perBankWrBursts::10 6248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5916 # Per bank write bursts -system.physmem.perBankWrBursts::12 6074 # Per bank write bursts -system.physmem.perBankWrBursts::13 6102 # Per bank write bursts -system.physmem.perBankWrBursts::14 6204 # Per bank write bursts -system.physmem.perBankWrBursts::15 6028 # Per bank write bursts +system.physmem.perBankWrBursts::11 5872 # Per bank write bursts +system.physmem.perBankWrBursts::12 6030 # Per bank write bursts +system.physmem.perBankWrBursts::13 6061 # Per bank write bursts +system.physmem.perBankWrBursts::14 6151 # Per bank write bursts +system.physmem.perBankWrBursts::15 5988 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33346162500 # Total gap between requests +system.physmem.totGap 33787609500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145193 # Read request sizes (log2) +system.physmem.readPktSize::6 152624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97768 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 41267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97338 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.437436 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.610569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.212794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52129 58.86% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22374 25.26% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4601 5.19% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1696 1.91% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1069 1.21% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 812 0.92% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 692 0.78% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 790 0.89% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4403 4.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5908 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.550271 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.061813 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.955752 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5907 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5908 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5908 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.543670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.503041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.228970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4711 79.74% 79.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.59% 80.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 768 13.00% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 163 2.76% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 108 1.83% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 1.03% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 38 0.64% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.17% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.17% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5908 # Writes before turning the bus around for reads -system.physmem.totQLat 7011292666 # Total ticks spent queuing -system.physmem.totMemAccLat 9731617666 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 725420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 48325.75 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 95484 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.396422 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.401782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 235.895158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59753 62.58% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22097 23.14% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4150 4.35% 90.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1579 1.65% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 956 1.00% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 842 0.88% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 589 0.62% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 882 0.92% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4636 4.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95484 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.058462 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.495488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5849 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5850 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5850 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.633846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.583273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.382653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4554 77.85% 77.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.43% 78.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 781 13.35% 91.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 204 3.49% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 105 1.79% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 84 1.44% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 47 0.80% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 32 0.55% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5850 # Writes before turning the bus around for reads +system.physmem.totQLat 6712073801 # Total ticks spent queuing +system.physmem.totMemAccLat 9570886301 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 762350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44022.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 67075.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 278.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 278.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62772.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 288.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 289.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.64 # Data bus utilization in percentage -system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.62 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.60 # Average write queue length when enqueuing -system.physmem.readRowHits 118088 # Number of row buffer hits during reads -system.physmem.writeRowHits 36158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.98 # Row buffer hit rate for writes -system.physmem.avgGap 137249.03 # Average gap between requests -system.physmem.pageHitRate 63.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342241200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186738750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583385400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 317818080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11790659475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9661917750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25060414575 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.639504 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15978647517 # Time in different power states -system.physmem_0.memoryStateTime::REF 1113320000 # Time in different power states +system.physmem.busUtil 3.70 # Data bus utilization in percentage +system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 121004 # Number of row buffer hits during reads +system.physmem.writeRowHits 33280 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.19 # Row buffer hit rate for writes +system.physmem.avgGap 135170.98 # Average gap between requests +system.physmem.pageHitRate 61.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 375641280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204963000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 625404000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 316826640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15342350850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6812703000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25884530610 # Total energy per rank (pJ) +system.physmem_0.averagePower 766.158096 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11227638574 # Time in different power states +system.physmem_0.memoryStateTime::REF 1128140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16249048233 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21429077176 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326909520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178373250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 547528800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315329760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11234568330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10149705000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24930068580 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.730472 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16793127980 # Time in different power states -system.physmem_1.memoryStateTime::REF 1113320000 # Time in different power states +system.physmem_1.actEnergy 346043880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 188813625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563401800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313625520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13705423425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8248614750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25572564840 # Total energy per rank (pJ) +system.physmem_1.averagePower 756.923807 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13625050098 # Time in different power states +system.physmem_1.memoryStateTime::REF 1128140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15434548270 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19031683152 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17208509 # Number of BP lookups -system.cpu.branchPred.condPredicted 11519539 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648302 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9342884 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675123 # Number of BTB hits +system.cpu.branchPred.lookups 17216173 # Number of BP lookups +system.cpu.branchPred.condPredicted 11524251 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650211 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9349330 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7678783 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.149398 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872388 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.131907 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872954 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101563 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,95 +412,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66692841 # number of cpu cycles simulated +system.cpu.numCycles 67575239 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5046776 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88195647 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17208509 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9547511 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60140641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322595 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6428 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13633 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22763338 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69414 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65868800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.694437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296898 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5134859 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88248834 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17216173 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9551737 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60707500 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1326839 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12635 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22778595 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 70008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.678669 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300955 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20089005 30.50% 30.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8265359 12.55% 43.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9198123 13.96% 57.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28316313 42.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20715769 31.14% 31.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8270385 12.43% 43.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9211836 13.85% 57.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28325800 42.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65868800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258026 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322416 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8616725 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19555814 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31576285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5627882 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492094 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179727 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171045 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101400911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3043244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492094 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13372904 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5353130 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 801467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32232883 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13616322 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99196979 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981006 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3848899 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 63135 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4311075 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5311261 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103921430 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457681852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115406862 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.305934 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8696241 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20116868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31576119 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5641245 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493317 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172097 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101426011 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3049995 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493317 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13462916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5983097 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 839028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32232549 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13512883 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99220100 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 979828 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3816376 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 66808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4343458 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5148151 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103925700 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457807646 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115438955 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 552 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10292204 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12699652 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24320213 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21993792 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1400092 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2341142 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98161647 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34523 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94891012 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 695609 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7513585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20245943 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65868800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.440606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149928 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10296474 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18669 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12740509 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24326602 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22004719 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1418947 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2350394 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98183255 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94912265 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694103 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7535192 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20267739 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66523790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.426742 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.152135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17598833 26.72% 26.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17429188 26.46% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17113322 25.98% 79.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11675618 17.73% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2050869 3.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 970 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18209770 27.37% 27.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17473699 26.27% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17129113 25.75% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11665460 17.54% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2044780 3.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 968 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65868800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66523790 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6712111 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6707680 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available @@ -527,13 +528,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11183885 37.33% 59.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12062879 40.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11186120 37.35% 59.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12052780 40.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49494737 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89878 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49503200 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89866 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -554,91 +555,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24064392 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21241967 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24070106 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21249051 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94891012 # Type of FU issued -system.cpu.iq.rate 1.422807 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29958914 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315719 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286305140 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105721004 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93462242 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124849808 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1363438 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94912265 # Type of FU issued +system.cpu.iq.rate 1.404542 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29946621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315519 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286988829 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105764420 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93479370 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124858764 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1365617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1453951 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2082 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1438054 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1460340 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2088 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11950 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1448981 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 138729 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 184462 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 137954 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492094 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 624554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 468032 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98206039 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493317 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 628934 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 513918 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98227667 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24320213 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21993792 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18603 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 463552 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302690 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221650 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524340 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93974044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23757485 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 916968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24326602 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22004719 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1669 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 509191 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11950 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303594 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221648 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525242 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93991933 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23762441 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9869 # number of nop insts executed -system.cpu.iew.exec_refs 44742217 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251815 # Number of branches executed -system.cpu.iew.exec_stores 20984732 # Number of stores executed -system.cpu.iew.exec_rate 1.409057 # Inst execution rate -system.cpu.iew.wb_sent 93584291 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93462299 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44972986 # num instructions producing a value -system.cpu.iew.wb_consumers 76550519 # num instructions consuming a value +system.cpu.iew.exec_nop 9890 # number of nop insts executed +system.cpu.iew.exec_refs 44753885 # number of memory reference insts executed +system.cpu.iew.exec_branches 14253415 # Number of branches executed +system.cpu.iew.exec_stores 20991444 # Number of stores executed +system.cpu.iew.exec_rate 1.390923 # Inst execution rate +system.cpu.iew.wb_sent 93601796 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93479432 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44975266 # num instructions producing a value +system.cpu.iew.wb_consumers 76559860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.401384 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587494 # average fanout of values written-back +system.cpu.iew.wb_rate 1.383339 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587452 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6533064 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6553334 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479099 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64811353 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.399263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.164401 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480109 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65462437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157754 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31214732 48.16% 48.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16807105 25.93% 74.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4339311 6.70% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4161583 6.42% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1937068 2.99% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1261836 1.95% 92.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 738743 1.14% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580049 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3770926 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31857215 48.66% 48.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16813031 25.68% 74.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4347273 6.64% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4157866 6.35% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1935310 2.96% 90.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1259510 1.92% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 744006 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 581672 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3766554 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64811353 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65462437 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,386 +685,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3770926 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158236329 # The number of ROB reads -system.cpu.rob.rob_writes 195501562 # The number of ROB writes -system.cpu.timesIdled 24613 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 824041 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3766554 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158912055 # The number of ROB reads +system.cpu.rob.rob_writes 195546008 # The number of ROB writes +system.cpu.timesIdled 28044 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1051449 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940559 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940559 # CPI: Total CPI of All Threads -system.cpu.ipc 1.063197 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.063197 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102271310 # number of integer regfile reads -system.cpu.int_regfile_writes 56791274 # number of integer regfile writes -system.cpu.fp_regfile_reads 36 # number of floating regfile reads -system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346086877 # number of cc regfile reads -system.cpu.cc_regfile_writes 38805113 # number of cc regfile writes -system.cpu.misc_regfile_reads 44208470 # number of misc regfile reads +system.cpu.cpi 0.953004 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.953004 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049314 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102290506 # number of integer regfile reads +system.cpu.int_regfile_writes 56802248 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 24 # number of floating regfile writes +system.cpu.cc_regfile_reads 346154538 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804906 # number of cc regfile writes +system.cpu.misc_regfile_reads 44219892 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485016 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.742621 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40419295 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.248124 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 152905500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.742621 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997544 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997544 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485017 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.752563 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40412566 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.234093 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.752563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997564 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84611982 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84611982 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21497006 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21497006 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830802 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830802 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60196 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60196 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15349 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15349 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84615901 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84615901 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21489624 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21489624 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831353 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831353 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60282 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60282 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15348 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15348 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40327808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40327808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40388004 # number of overall hits -system.cpu.dcache.overall_hits::total 40388004 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 555640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 555640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019099 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68639 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68639 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40320977 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40320977 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40381259 # number of overall hits +system.cpu.dcache.overall_hits::total 40381259 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564963 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564963 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018548 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018548 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68572 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68572 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1574739 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1574739 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1643378 # number of overall misses -system.cpu.dcache.overall_misses::total 1643378 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9002363000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9002363000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14580629410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14580629410 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5329000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5329000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23582992410 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23582992410 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23582992410 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23582992410 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22052646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22052646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1583511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1652083 # number of overall misses +system.cpu.dcache.overall_misses::total 1652083 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9256149500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9256149500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14245975429 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14245975429 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5465000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5465000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23502124929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23502124929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23502124929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23502124929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054587 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054587 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128835 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128835 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128854 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128854 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15925 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41902547 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41902547 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42031382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42031382 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025196 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025196 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051340 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051340 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532767 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532767 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036230 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036230 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039099 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039099 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16201.790728 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16201.790728 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14307.372895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14307.372895 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9235.701906 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9235.701906 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14975.810220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14975.810220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14350.315271 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14350.315271 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3096615 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130248 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.833333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.774760 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904488 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033342 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033342 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025617 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025617 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051312 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051312 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532168 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532168 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037789 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037789 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039304 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039304 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9471.403813 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9471.403813 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14841.781919 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14225.753143 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2896869 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131288 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.466667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.064995 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 253749 # number of writebacks -system.cpu.dcache.writebacks::total 253749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256216 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 256216 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870580 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870580 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 485017 # number of writebacks +system.cpu.dcache.writebacks::total 485017 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265550 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 265550 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870019 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870019 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 577 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1126796 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1126796 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1126796 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1126796 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299424 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148519 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485538 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485538 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3220458500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3220458500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2349684961 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2349684961 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2014368500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2014368500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5570143461 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5570143461 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7584511961 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7584511961 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013578 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013578 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1135569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135569 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135569 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148529 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148529 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447942 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447942 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485539 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485539 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3625766000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3625766000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2305447971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2305447971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1884857000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1884857000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5931213971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5931213971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291780 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10755.512250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10755.512250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.770144 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.770144 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53580.755420 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53580.755420 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12434.938064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12434.938064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15620.841131 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15620.841131 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322602 # number of replacements -system.cpu.icache.tags.tagsinuse 510.289801 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22429330 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323114 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.416150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1108313500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.289801 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996660 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996660 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 323105 # number of replacements +system.cpu.icache.tags.tagsinuse 510.281102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22444187 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323617 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.354166 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.281102 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996643 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996643 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 350 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 341 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45849556 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45849556 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22429330 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22429330 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22429330 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22429330 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22429330 # number of overall hits -system.cpu.icache.overall_hits::total 22429330 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 333886 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 333886 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 333886 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 333886 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 333886 # number of overall misses -system.cpu.icache.overall_misses::total 333886 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3387462898 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3387462898 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3387462898 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3387462898 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3387462898 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3387462898 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22763216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22763216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22763216 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22763216 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22763216 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22763216 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014668 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014668 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014668 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10145.567343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10145.567343 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10145.567343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10145.567343 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 275055 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45880575 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45880575 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22444187 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22444187 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22444187 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22444187 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22444187 # number of overall hits +system.cpu.icache.overall_hits::total 22444187 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334287 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334287 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334287 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334287 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334287 # number of overall misses +system.cpu.icache.overall_misses::total 334287 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3550514898 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3550514898 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3550514898 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3550514898 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3550514898 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3550514898 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22778474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22778474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22778474 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22778474 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22778474 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22778474 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10621.157562 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10621.157562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10621.157562 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 261417 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16465 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16440 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.705436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.901277 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10762 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 10762 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 10762 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 10762 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 10762 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 10762 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323124 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323124 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323124 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323124 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323124 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323124 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3106237439 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3106237439 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3106237439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3106237439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3106237439 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3106237439 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014195 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014195 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014195 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9613.143682 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9613.143682 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9613.143682 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9613.143682 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9613.143682 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9613.143682 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 323105 # number of writebacks +system.cpu.icache.writebacks::total 323105 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10659 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10659 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10659 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 10659 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 10659 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 10659 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3274041434 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3274041434 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3274041434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3274041434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3274041434 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3274041434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014208 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014208 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014208 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10116.681604 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10116.681604 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 824554 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825997 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 1265 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 822385 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826178 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3328 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78883 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 129320 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16077.798328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1332136 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 145605 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.148972 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78886 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 128056 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15991.461548 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1186413 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 144416 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.215246 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 12580.729391 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1435.218060 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1954.277207 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.573670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.767867 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087599 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.119280 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.981311 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 27 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16258 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2698 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11935 # 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number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 107 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 107 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3307 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3334 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3307 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3334 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112837 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112837 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8287 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8287 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 11515 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 11515 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 36313 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 36313 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 11515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 44600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 56115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 11515 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 44600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112837 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168952 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10338050198 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 173000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 173000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 653811000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 653811000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 801316000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 801316000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2775072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2775072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801316000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3428883500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4230199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801316000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3428883500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14568249698 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092103 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092103 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059915 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.035582 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.107764 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.107764 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.198976 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94466.292379 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17333.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17333.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80754.565113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80754.565113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71826.512651 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71826.512651 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80537.939812 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80537.939812 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78940.753354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89791.262138 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208803 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1616280 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 807659 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 20376 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 20194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 351517 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 505600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 141126 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 1617289 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808162 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79873 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67046 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10433 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 350764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 474834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 78545 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142478 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323124 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336969 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2345110 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20679232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47313728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 67992960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 270457 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1886726 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.095537 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.294284 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336967 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 939793 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2346582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39434560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 58959360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 98393920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318372 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1127528 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.139590 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.372305 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1706655 90.46% 90.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 179889 9.53% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 182 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980569 86.97% 86.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136526 12.11% 99.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10433 0.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1886726 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1061889000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485111148 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728499095 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1127528 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 485882115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 728582930 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 136869 # Transaction distribution -system.membus.trans_dist::Writeback 97768 # Transaction distribution -system.membus.trans_dist::CleanEvict 30364 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8324 # Transaction distribution -system.membus.trans_dist::ReadExResp 8324 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 136869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 418530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15549504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15549504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 144336 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97338 # Transaction distribution +system.membus.trans_dist::CleanEvict 27827 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10 # Transaction distribution +system.membus.trans_dist::ReadExReq 8287 # Transaction distribution +system.membus.trans_dist::ReadExResp 8287 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144337 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 430432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 430432 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15997504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15997504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 273331 # Request fanout histogram +system.membus.snoop_fanout::samples 277799 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 273331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 277799 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 273331 # Request fanout histogram -system.membus.reqLayer0.occupancy 739892708 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 277799 # Request fanout histogram +system.membus.reqLayer0.occupancy 747949896 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 756443702 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 797228853 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |