diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1274 |
1 files changed, 637 insertions, 637 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index f9d46e356..ba9e20c75 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025579 # Number of seconds simulated -sim_ticks 25578679000 # Number of ticks simulated -final_tick 25578679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025535 # Number of seconds simulated +sim_ticks 25534556000 # Number of ticks simulated +final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106593 # Simulator instruction rate (inst/s) -host_op_rate 151269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38451628 # Simulator tick rate (ticks/s) -host_mem_usage 298528 # Number of bytes of host memory used -host_seconds 665.22 # Real time elapsed on the host +host_inst_rate 42425 # Simulator instruction rate (inst/s) +host_op_rate 60207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15277801 # Simulator tick rate (ticks/s) +host_mem_usage 296924 # Number of bytes of host memory used +host_seconds 1671.35 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11654707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 310553645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322208352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11654707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11654707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210029924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210029924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210029924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11654707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 310553645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 532238275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128777 # Total number of read requests seen -system.physmem.writeReqs 83942 # Total number of write requests seen -system.physmem.cpureqs 213038 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241664 # Total number of bytes read from memory -system.physmem.bytesWritten 5372288 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 311085260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322737548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 311085260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 533137917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128766 # Total number of read requests seen +system.physmem.writeReqs 83945 # Total number of write requests seen +system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8240960 # Total number of bytes read from memory +system.physmem.bytesWritten 5372480 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8240960 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7986 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8007 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7985 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7981 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 8125 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7948 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5374 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25578660500 # Total gap between requests +system.physmem.totGap 25534539500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128777 # Categorize read packet sizes +system.physmem.readPktSize::6 128766 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83942 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83945 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,10 +124,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3638 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see @@ -139,53 +139,53 @@ system.physmem.wrQLenPdf::11 3650 # Wh system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3210060500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5252104250 # Sum of mem lat for all requests -system.physmem.totBusLat 643875000 # Total cycles spent in databus access -system.physmem.totBankLat 1398168750 # Total cycles spent in bank access -system.physmem.avgQLat 24927.67 # Average queueing delay per request -system.physmem.avgBankLat 10857.45 # Average bank access latency per request +system.physmem.totQLat 3209266500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5253345250 # Sum of mem lat for all requests +system.physmem.totBusLat 643820000 # Total cycles spent in databus access +system.physmem.totBankLat 1400258750 # Total cycles spent in bank access +system.physmem.avgQLat 24923.63 # Average queueing delay per request +system.physmem.avgBankLat 10874.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40785.12 # Average memory access latency -system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 210.03 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 40798.25 # Average memory access latency +system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 210.40 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.16 # Data bus utilization in percentage +system.physmem.busUtil 4.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.21 # Average read queue length over time -system.physmem.avgWrQLen 9.59 # Average write queue length over time -system.physmem.readRowHits 116755 # Number of row buffer hits during reads -system.physmem.writeRowHits 52878 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes -system.physmem.avgGap 120246.24 # Average gap between requests -system.cpu.branchPred.lookups 16623550 # Number of BP lookups -system.cpu.branchPred.condPredicted 12760225 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602776 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10462790 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7764993 # Number of BTB hits +system.physmem.avgWrQLen 9.90 # Average write queue length over time +system.physmem.readRowHits 116738 # Number of row buffer hits during reads +system.physmem.writeRowHits 52892 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes +system.physmem.avgGap 120043.34 # Average gap between requests +system.cpu.branchPred.lookups 16612549 # Number of BP lookups +system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10534593 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7757405 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.215319 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825730 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.637444 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1822464 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113740 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51157359 # number of cpu cycles simulated +system.cpu.numCycles 51069113 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12528196 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85178151 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16623550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9590723 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21186766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2362966 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10580824 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 65 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 592 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11675240 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179625 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46030286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591135 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335079 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12514698 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10532726 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11663165 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178973 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 45949088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.594403 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24863758 54.02% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2136664 4.64% 58.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1964751 4.27% 62.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042058 4.44% 67.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1465237 3.18% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1378794 3.00% 73.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958007 2.08% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1192757 2.59% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10028260 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24794811 53.96% 53.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137100 4.65% 58.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1960912 4.27% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2040333 4.44% 67.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467005 3.19% 70.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1375299 2.99% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 957293 2.08% 75.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1188429 2.59% 78.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10027906 21.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46030286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324949 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.665022 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14611843 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8929429 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19464778 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1393400 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1630836 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3329843 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104767 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116826409 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 364015 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1630836 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16323672 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2560343 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 881200 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19095931 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5538304 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114955778 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16357 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4684077 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115266627 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529628092 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529622760 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14598305 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8880724 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3327841 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105063 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16304725 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 873067 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 145 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17204 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4661371 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115217977 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529361609 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529355204 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6405 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16133955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20202 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20198 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13085199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29620303 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22433978 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3897320 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4410132 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111515414 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35833 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107233709 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271611 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10777789 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25822592 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2047 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46030286 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.329634 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.987559 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16085305 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20097 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20095 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13032825 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29592002 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22430174 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3871274 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107205683 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272681 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25689486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 45949088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10772482 23.40% 23.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8089494 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7436899 16.16% 57.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7132502 15.50% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5411548 11.76% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3908660 8.49% 92.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839023 4.00% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 868143 1.89% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571535 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10727081 23.35% 23.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8071190 17.57% 40.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7423915 16.16% 57.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5405073 11.76% 84.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3914653 8.52% 92.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842463 4.01% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 872331 1.90% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 570973 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46030286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 45949088 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112260 4.55% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1357456 55.03% 59.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 996870 40.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112030 4.53% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1365116 55.14% 59.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 998484 40.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56624482 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91603 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56613299 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28897893 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21619537 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107233709 # Type of FU issued -system.cpu.iq.rate 2.096154 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2466586 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023002 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263235386 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122356888 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105553525 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109700035 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179098 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107205683 # Type of FU issued +system.cpu.iq.rate 2.099227 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2475632 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263108179 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105531184 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109681022 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2313195 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6752 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29821 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1878240 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2284894 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30581 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1874436 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 495 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1630836 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1047773 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45606 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111560996 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 293586 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29620303 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22433978 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19913 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6800 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5244 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29821 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391475 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181717 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573192 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106207305 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28598865 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1026404 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1623237 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1048241 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45255 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111511491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29592002 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22430174 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19843 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6298 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5233 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30581 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106181677 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28584422 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1024006 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9749 # number of nop insts executed -system.cpu.iew.exec_refs 49933799 # number of memory reference insts executed -system.cpu.iew.exec_branches 14599943 # Number of branches executed -system.cpu.iew.exec_stores 21334934 # Number of stores executed -system.cpu.iew.exec_rate 2.076090 # Inst execution rate -system.cpu.iew.wb_sent 105772568 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105553695 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53290851 # num instructions producing a value -system.cpu.iew.wb_consumers 103571318 # num instructions consuming a value +system.cpu.iew.exec_nop 9768 # number of nop insts executed +system.cpu.iew.exec_refs 49919694 # number of memory reference insts executed +system.cpu.iew.exec_branches 14596236 # Number of branches executed +system.cpu.iew.exec_stores 21335272 # Number of stores executed +system.cpu.iew.exec_rate 2.079176 # Inst execution rate +system.cpu.iew.wb_sent 105750985 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105531355 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53247115 # num instructions producing a value +system.cpu.iew.wb_consumers 103478593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.063314 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back +system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514571 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10929447 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10879947 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499822 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44399450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764020 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 496884 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44325851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.270288 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.765576 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15322466 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11640372 26.22% 60.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3466304 7.81% 68.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2879944 6.49% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880994 4.24% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1947998 4.39% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685125 1.54% 85.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565076 1.27% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6011171 13.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11622337 26.22% 60.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3461272 7.81% 68.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2876318 6.49% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875937 4.23% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1955484 4.41% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6014208 13.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44399450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44325851 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,204 +472,204 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6011171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6014208 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149924855 # The number of ROB reads -system.cpu.rob.rob_writes 224763597 # The number of ROB writes -system.cpu.timesIdled 74024 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5127073 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149798719 # The number of ROB reads +system.cpu.rob.rob_writes 224657070 # The number of ROB writes +system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.721465 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.721465 # CPI: Total CPI of All Threads -system.cpu.ipc 1.386069 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.386069 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511541679 # number of integer regfile reads -system.cpu.int_regfile_writes 103323268 # number of integer regfile writes -system.cpu.fp_regfile_reads 788 # number of floating regfile reads -system.cpu.fp_regfile_writes 660 # number of floating regfile writes -system.cpu.misc_regfile_reads 49173958 # number of misc regfile reads +system.cpu.cpi 0.720220 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads +system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511419514 # number of integer regfile reads +system.cpu.int_regfile_writes 103305187 # number of integer regfile writes +system.cpu.fp_regfile_reads 846 # number of floating regfile reads +system.cpu.fp_regfile_writes 738 # number of floating regfile writes +system.cpu.misc_regfile_reads 49163804 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 28620 # number of replacements -system.cpu.icache.tagsinuse 1814.215623 # Cycle average of tags in use -system.cpu.icache.total_refs 11640482 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.713009 # Average number of references to valid blocks. +system.cpu.icache.replacements 28595 # number of replacements +system.cpu.icache.tagsinuse 1814.564534 # Cycle average of tags in use +system.cpu.icache.total_refs 11628419 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30629 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379.653890 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.215623 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885847 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885847 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11640487 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11640487 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11640487 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11640487 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11640487 # number of overall hits -system.cpu.icache.overall_hits::total 11640487 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34753 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34753 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34753 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34753 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34753 # number of overall misses -system.cpu.icache.overall_misses::total 34753 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 732473500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 732473500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 732473500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 732473500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 732473500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 732473500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11675240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11675240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11675240 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11675240 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11675240 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11675240 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002977 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002977 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002977 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002977 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002977 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002977 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21076.554542 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21076.554542 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21076.554542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21076.554542 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 767 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1814.564534 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.886018 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.886018 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11628429 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11628429 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11628429 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11628429 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11628429 # number of overall hits +system.cpu.icache.overall_hits::total 11628429 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34736 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34736 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34736 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34736 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34736 # number of overall misses +system.cpu.icache.overall_misses::total 34736 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739851499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739851499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739851499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739851499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739851499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739851499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11663165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11663165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11663165 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11663165 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11663165 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11663165 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002978 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002978 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002978 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.271620 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21299.271620 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.271620 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21299.271620 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.271620 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21299.271620 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1371 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.958333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65.285714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3764 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3764 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3764 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3764 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3764 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3764 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30989 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 30989 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 30989 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 30989 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 30989 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 30989 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 594730000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 594730000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 594730000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 594730000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 594730000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 594730000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002654 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002654 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002654 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19191.648650 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19191.648650 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19191.648650 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19191.648650 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19191.648650 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19191.648650 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3776 # 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number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3199316 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5395861980 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5395861980 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245320540 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606004493 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6851325033 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245320540 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606004493 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6851325033 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394710 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308652 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.943787 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.943787 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955423 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955423 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764212 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.667411 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764212 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.667411 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52655.192101 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55356.228581 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54881.713914 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.203762 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.203762 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52767.653853 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52767.653853 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52655.192101 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52655.192101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 128767 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250601778 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209164905 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1459766683 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3249822 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3249822 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5391078264 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5391078264 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250601778 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6600243169 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6850844947 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250601778 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6600243169 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6850844947 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394982 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309055 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955313 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955313 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764292 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.667771 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764292 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.667771 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53904.447838 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55296.332602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55052.296085 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.314815 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.314815 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52723.966162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52723.966162 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53177.163417 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.421273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53177.163417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.421273 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158317 # number of replacements -system.cpu.dcache.tagsinuse 4072.315940 # Cycle average of tags in use -system.cpu.dcache.total_refs 44364640 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162413 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.159415 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315940 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26064832 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26064832 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267213 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits +system.cpu.dcache.replacements 158299 # number of replacements +system.cpu.dcache.tagsinuse 4072.272113 # Cycle average of tags in use +system.cpu.dcache.total_refs 44344927 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162395 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.068303 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 284501000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.272113 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994207 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994207 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26045311 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26045311 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15985 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15985 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44332045 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44332045 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44332045 # number of overall hits -system.cpu.dcache.overall_hits::total 44332045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582688 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582688 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707105 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707105 # number of overall misses -system.cpu.dcache.overall_misses::total 1707105 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247904000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4247904000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98406408482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98406408482 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102654312482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102654312482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102654312482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102654312482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26189249 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26189249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44312366 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44312366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44312366 # number of overall hits +system.cpu.dcache.overall_hits::total 44312366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124674 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124674 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582846 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707520 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707520 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707520 # number of overall misses +system.cpu.dcache.overall_misses::total 1707520 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4256897000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4256897000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98390757481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98390757481 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 860000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 860000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102647654481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102647654481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102647654481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102647654481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26169985 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26169985 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16031 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16031 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46039150 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46039150 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46039150 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46039150 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079733 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079733 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002807 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002807 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037079 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037079 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037079 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34142.472492 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34142.472492 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62176.757821 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62176.757821 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60133.566759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60133.566759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5187 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46019886 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46019886 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46019886 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46019886 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079741 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079741 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002621 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002621 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037104 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037104 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037104 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037104 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34144.224137 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34144.224137 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.663439 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.663439 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.052521 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60115.052521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.052521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60115.052521 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3743 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 131 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.516393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.572519 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129090 # number of writebacks -system.cpu.dcache.writebacks::total 129090 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69000 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69000 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475354 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475354 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107334 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107334 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162751 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162751 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162751 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162751 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6813869491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6813869491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8692535991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8692535991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8692535991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8692535991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33900.544959 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33900.544959 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63482.861824 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63482.861824 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129075 # number of writebacks +system.cpu.dcache.writebacks::total 129075 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69278 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69278 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475504 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544782 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544782 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544782 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544782 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55396 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55396 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107342 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107342 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162738 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162738 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878391000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878391000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809216990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809216990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687607990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8687607990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687607990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8687607990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33908.422991 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33908.422991 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.787781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.787781 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |