diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1661 |
1 files changed, 828 insertions, 833 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index b6f1be7c5..56872871d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033788 # Number of seconds simulated -sim_ticks 33787619000 # Number of ticks simulated -final_tick 33787619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033784 # Number of seconds simulated +sim_ticks 33784139000 # Number of ticks simulated +final_tick 33784139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117892 # Simulator instruction rate (inst/s) -host_op_rate 150770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56175899 # Simulator tick rate (ticks/s) -host_mem_usage 326928 # Number of bytes of host memory used -host_seconds 601.46 # Real time elapsed on the host +host_inst_rate 118438 # Simulator instruction rate (inst/s) +host_op_rate 151468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56430150 # Simulator tick rate (ticks/s) +host_mem_usage 329476 # Number of bytes of host memory used +host_seconds 598.69 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 736896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2854400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6176576 # Number of bytes read from this memory -system.physmem.bytes_read::total 9767872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 736896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 736896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6229632 # Number of bytes written to this memory -system.physmem.bytes_written::total 6229632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 11514 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 44600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96509 # Number of read requests responded to by this memory -system.physmem.num_reads::total 152623 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97338 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21809646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 84480650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 182805897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 289096192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21809646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21809646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 184376176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 184376176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 184376176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21809646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 84480650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 182805897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 473472369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 152624 # Number of read requests accepted -system.physmem.writeReqs 97338 # Number of write requests accepted -system.physmem.readBursts 152624 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97338 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9758080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6227712 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9767936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6229632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 27837 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9027 # Per bank write bursts -system.physmem.perBankRdBursts::1 9355 # Per bank write bursts -system.physmem.perBankRdBursts::2 9548 # Per bank write bursts -system.physmem.perBankRdBursts::3 12185 # Per bank write bursts -system.physmem.perBankRdBursts::4 10599 # Per bank write bursts -system.physmem.perBankRdBursts::5 10432 # Per bank write bursts -system.physmem.perBankRdBursts::6 9787 # Per bank write bursts -system.physmem.perBankRdBursts::7 9285 # Per bank write bursts -system.physmem.perBankRdBursts::8 9499 # Per bank write bursts -system.physmem.perBankRdBursts::9 9569 # Per bank write bursts -system.physmem.perBankRdBursts::10 9134 # Per bank write bursts -system.physmem.perBankRdBursts::11 8776 # Per bank write bursts -system.physmem.perBankRdBursts::12 8706 # Per bank write bursts -system.physmem.perBankRdBursts::13 8772 # Per bank write bursts -system.physmem.perBankRdBursts::14 8686 # Per bank write bursts -system.physmem.perBankRdBursts::15 9110 # Per bank write bursts -system.physmem.perBankWrBursts::0 5979 # Per bank write bursts -system.physmem.perBankWrBursts::1 6226 # Per bank write bursts -system.physmem.perBankWrBursts::2 6146 # Per bank write bursts -system.physmem.perBankWrBursts::3 6158 # Per bank write bursts -system.physmem.perBankWrBursts::4 6081 # Per bank write bursts -system.physmem.perBankWrBursts::5 6325 # Per bank write bursts -system.physmem.perBankWrBursts::6 6021 # Per bank write bursts -system.physmem.perBankWrBursts::7 5966 # Per bank write bursts -system.physmem.perBankWrBursts::8 5954 # Per bank write bursts -system.physmem.perBankWrBursts::9 6102 # Per bank write bursts -system.physmem.perBankWrBursts::10 6248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5872 # Per bank write bursts -system.physmem.perBankWrBursts::12 6030 # Per bank write bursts -system.physmem.perBankWrBursts::13 6061 # Per bank write bursts -system.physmem.perBankWrBursts::14 6151 # Per bank write bursts -system.physmem.perBankWrBursts::15 5988 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 781248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2836288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6167232 # Number of bytes read from this memory +system.physmem.bytes_read::total 9784768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 781248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 781248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6226432 # Number of bytes written to this memory +system.physmem.bytes_written::total 6226432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 12207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97288 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97288 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 23124698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 83953242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 182548148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 289626088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 23124698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 23124698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184300449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184300449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184300449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 23124698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 83953242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 182548148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 473926537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 152888 # Number of read requests accepted +system.physmem.writeReqs 97288 # Number of write requests accepted +system.physmem.readBursts 152888 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97288 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9777152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 6224960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9784832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6226432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9124 # Per bank write bursts +system.physmem.perBankRdBursts::1 9348 # Per bank write bursts +system.physmem.perBankRdBursts::2 9757 # Per bank write bursts +system.physmem.perBankRdBursts::3 12566 # Per bank write bursts +system.physmem.perBankRdBursts::4 10929 # Per bank write bursts +system.physmem.perBankRdBursts::5 10090 # Per bank write bursts +system.physmem.perBankRdBursts::6 9786 # Per bank write bursts +system.physmem.perBankRdBursts::7 8974 # Per bank write bursts +system.physmem.perBankRdBursts::8 9178 # Per bank write bursts +system.physmem.perBankRdBursts::9 9832 # Per bank write bursts +system.physmem.perBankRdBursts::10 9165 # Per bank write bursts +system.physmem.perBankRdBursts::11 8819 # Per bank write bursts +system.physmem.perBankRdBursts::12 8693 # Per bank write bursts +system.physmem.perBankRdBursts::13 8672 # Per bank write bursts +system.physmem.perBankRdBursts::14 8813 # Per bank write bursts +system.physmem.perBankRdBursts::15 9022 # Per bank write bursts +system.physmem.perBankWrBursts::0 5950 # Per bank write bursts +system.physmem.perBankWrBursts::1 6192 # Per bank write bursts +system.physmem.perBankWrBursts::2 6162 # Per bank write bursts +system.physmem.perBankWrBursts::3 6171 # Per bank write bursts +system.physmem.perBankWrBursts::4 6089 # Per bank write bursts +system.physmem.perBankWrBursts::5 6262 # Per bank write bursts +system.physmem.perBankWrBursts::6 6013 # Per bank write bursts +system.physmem.perBankWrBursts::7 5971 # Per bank write bursts +system.physmem.perBankWrBursts::8 5978 # Per bank write bursts +system.physmem.perBankWrBursts::9 6080 # Per bank write bursts +system.physmem.perBankWrBursts::10 6215 # Per bank write bursts +system.physmem.perBankWrBursts::11 5915 # Per bank write bursts +system.physmem.perBankWrBursts::12 6050 # Per bank write bursts +system.physmem.perBankWrBursts::13 6057 # Per bank write bursts +system.physmem.perBankWrBursts::14 6142 # Per bank write bursts +system.physmem.perBankWrBursts::15 6018 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33787609500 # Total gap between requests +system.physmem.totGap 33784127500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152624 # Read request sizes (log2) +system.physmem.readPktSize::6 152888 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97338 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97288 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 50168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 39 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,103 +197,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95484 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 167.396422 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 105.401782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 235.895158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59753 62.58% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22097 23.14% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4150 4.35% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1579 1.65% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 956 1.00% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 842 0.88% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 589 0.62% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 882 0.92% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4636 4.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95484 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5850 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.058462 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.495488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5849 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 95539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.474225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.587098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 235.887781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59486 62.26% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22475 23.52% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4141 4.33% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1560 1.63% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 915 0.96% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 855 0.89% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 603 0.63% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 793 0.83% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4711 4.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95539 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5851 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.107332 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.473486 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5850 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5850 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5850 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.633846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.583273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.382653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4554 77.85% 77.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.43% 78.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 781 13.35% 91.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 204 3.49% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 105 1.79% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 84 1.44% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 47 0.80% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 32 0.55% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5850 # Writes before turning the bus around for reads -system.physmem.totQLat 6712073801 # Total ticks spent queuing -system.physmem.totMemAccLat 9570886301 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 762350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44022.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5851 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5851 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.623654 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.576655 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.320793 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4551 77.78% 77.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.51% 78.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 752 12.85% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 225 3.85% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 138 2.36% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 80 1.37% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 45 0.77% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.38% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5851 # Writes before turning the bus around for reads +system.physmem.totQLat 6694958033 # Total ticks spent queuing +system.physmem.totMemAccLat 9559358033 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 763840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43824.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62772.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 288.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 184.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 289.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 184.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62574.35 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 289.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 289.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.70 # Data bus utilization in percentage system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 121004 # Number of row buffer hits during reads -system.physmem.writeRowHits 33280 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.19 # Row buffer hit rate for writes -system.physmem.avgGap 135170.98 # Average gap between requests -system.physmem.pageHitRate 61.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 375641280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204963000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 625404000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 316826640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15342350850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6812703000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25884530610 # Total energy per rank (pJ) -system.physmem_0.averagePower 766.158096 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11227638574 # Time in different power states -system.physmem_0.memoryStateTime::REF 1128140000 # Time in different power states +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 121417 # Number of row buffer hits during reads +system.physmem.writeRowHits 33065 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.99 # Row buffer hit rate for writes +system.physmem.avgGap 135041.44 # Average gap between requests +system.physmem.pageHitRate 61.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 374855040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204534000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 627829800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 316068480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15176758725 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6953261250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25859440575 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.592889 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11461051997 # Time in different power states +system.physmem_0.memoryStateTime::REF 1127880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21429077176 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21188094253 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 346043880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 188813625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563401800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313625520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13705423425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8248614750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25572564840 # Total energy per rank (pJ) -system.physmem_1.averagePower 756.923807 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13625050098 # Time in different power states -system.physmem_1.memoryStateTime::REF 1128140000 # Time in different power states +system.physmem_1.actEnergy 346777200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189213750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562754400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313787520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13818315060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8144878500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25581859710 # Total energy per rank (pJ) +system.physmem_1.averagePower 757.374848 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13453093141 # Time in different power states +system.physmem_1.memoryStateTime::REF 1127880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19031683152 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19196289859 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17216173 # Number of BP lookups -system.cpu.branchPred.condPredicted 11524251 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 650211 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9349330 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7678783 # Number of BTB hits +system.cpu.branchPred.lookups 17214384 # Number of BP lookups +system.cpu.branchPred.condPredicted 11522342 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650449 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9351216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7679376 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.131907 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872954 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101563 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.121683 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872997 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,129 +408,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 67575239 # number of cpu cycles simulated +system.cpu.numCycles 67568279 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5134859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88248834 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17216173 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9551737 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60707500 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1326839 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5160872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88245051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17214384 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9552373 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60651743 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1327287 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6028 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12635 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22778595 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 70008 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66523790 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.678669 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300955 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 12780 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22780660 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66495093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.679326 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300807 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20715769 31.14% 31.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8270385 12.43% 43.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9211836 13.85% 57.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28325800 42.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20690371 31.12% 31.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8267529 12.43% 43.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9212157 13.85% 57.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28325036 42.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 66495093 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.305934 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8696241 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20116868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31576119 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5641245 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 493317 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3182236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172097 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101426011 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3049995 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 493317 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13462916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5983097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 839028 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32232549 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13512883 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99220100 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 979828 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3816376 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 66808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4343458 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5148151 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103925700 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457807646 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115438955 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 552 # Number of floating rename lookups +system.cpu.fetch.rate 1.306013 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8713541 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20066003 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31587262 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5634718 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493569 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182821 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172049 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101434518 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3052676 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493569 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13478922 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5884192 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 838725 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32239032 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13560653 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99228097 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981180 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3845119 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4384146 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5165586 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103939784 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457840373 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115445962 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10296474 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18669 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 10310558 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12740509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24326602 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22004719 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1418947 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2350394 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98183255 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94912265 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694103 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7535192 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20267739 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66523790 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.426742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152135 # Number of insts issued each cycle +system.cpu.rename.skidInsts 12730367 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24327975 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22005134 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1415958 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2369050 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98190630 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34517 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94916965 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 695759 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7542562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20296667 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66495093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.427428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18209770 27.37% 27.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17473699 26.27% 53.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17129113 25.75% 79.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11665460 17.54% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2044780 3.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 968 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18174968 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17486428 26.30% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17117325 25.74% 79.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11670567 17.55% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2044839 3.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 966 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66523790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66495093 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6707680 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11186120 37.35% 59.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12052780 40.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6711532 22.43% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11180045 37.36% 59.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12034310 40.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49503200 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89866 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49505832 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89861 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -555,89 +551,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24070106 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21249051 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24073706 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21247526 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94912265 # Type of FU issued -system.cpu.iq.rate 1.404542 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29946621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315519 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286988829 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105764420 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93479370 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124858764 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1365617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94916965 # Type of FU issued +system.cpu.iq.rate 1.404756 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29925928 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315285 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286950501 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105779157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93480434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124842774 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1366701 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1460340 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2088 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11950 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1448981 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1461713 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2105 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1449396 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 137954 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185768 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140491 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185859 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 493317 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 628934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 513918 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98227667 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493569 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 630289 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 523749 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98235038 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24326602 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22004719 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1669 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 509191 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11950 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303594 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221648 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 525242 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93991933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23762441 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 920332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24327975 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22005134 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18597 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1652 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 519239 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303965 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221737 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525702 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93996105 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23765772 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9890 # number of nop insts executed -system.cpu.iew.exec_refs 44753885 # number of memory reference insts executed -system.cpu.iew.exec_branches 14253415 # Number of branches executed -system.cpu.iew.exec_stores 20991444 # Number of stores executed -system.cpu.iew.exec_rate 1.390923 # Inst execution rate -system.cpu.iew.wb_sent 93601796 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93479432 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44975266 # num instructions producing a value -system.cpu.iew.wb_consumers 76559860 # num instructions consuming a value -system.cpu.iew.wb_rate 1.383339 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587452 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6553334 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9891 # number of nop insts executed +system.cpu.iew.exec_refs 44755693 # number of memory reference insts executed +system.cpu.iew.exec_branches 14254152 # Number of branches executed +system.cpu.iew.exec_stores 20989921 # Number of stores executed +system.cpu.iew.exec_rate 1.391128 # Inst execution rate +system.cpu.iew.wb_sent 93602702 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93480493 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44980132 # num instructions producing a value +system.cpu.iew.wb_consumers 76556790 # num instructions consuming a value +system.cpu.iew.wb_rate 1.383497 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587539 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6559945 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 480109 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65462437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.385346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157754 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480375 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65432608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31857215 48.66% 48.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16813031 25.68% 74.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4347273 6.64% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4157866 6.35% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935310 2.96% 90.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1259510 1.92% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 744006 1.14% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 581672 0.89% 94.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3766554 5.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31819625 48.63% 48.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16816004 25.70% 74.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4349451 6.65% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4164400 6.36% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1932309 2.95% 90.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1260445 1.93% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 747040 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580342 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3762992 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65462437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65432608 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -683,386 +679,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3766554 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158912055 # The number of ROB reads -system.cpu.rob.rob_writes 195546008 # The number of ROB writes -system.cpu.timesIdled 28044 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1051449 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3762992 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158892399 # The number of ROB reads +system.cpu.rob.rob_writes 195560325 # The number of ROB writes +system.cpu.timesIdled 28658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1073186 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.953004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.953004 # CPI: Total CPI of All Threads -system.cpu.ipc 1.049314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102290506 # number of integer regfile reads -system.cpu.int_regfile_writes 56802248 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 24 # number of floating regfile writes -system.cpu.cc_regfile_reads 346154538 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804906 # number of cc regfile writes -system.cpu.misc_regfile_reads 44219892 # number of misc regfile reads +system.cpu.cpi 0.952906 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.952906 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102292430 # number of integer regfile reads +system.cpu.int_regfile_writes 56802415 # number of integer regfile writes +system.cpu.fp_regfile_reads 38 # number of floating regfile reads +system.cpu.fp_regfile_writes 22 # number of floating regfile writes +system.cpu.cc_regfile_reads 346166780 # number of cc regfile reads +system.cpu.cc_regfile_writes 38809001 # number of cc regfile writes +system.cpu.misc_regfile_reads 44218310 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485017 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.752563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40412566 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.234093 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 485025 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.752435 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40412261 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485537 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.232094 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.752563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 510.752435 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997563 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997563 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 455 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84615901 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84615901 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21489624 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21489624 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831353 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831353 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60282 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60282 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15348 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15348 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84614979 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84614979 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21489272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21489272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831416 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831416 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60267 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60267 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15347 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15347 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40320977 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40320977 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40381259 # number of overall hits -system.cpu.dcache.overall_hits::total 40381259 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 564963 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 564963 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018548 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018548 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68572 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68572 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1583511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1583511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1652083 # number of overall misses -system.cpu.dcache.overall_misses::total 1652083 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9256149500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9256149500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14245975429 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14245975429 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5465000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5465000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23502124929 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23502124929 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23502124929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23502124929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054587 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054587 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40320688 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40320688 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40380955 # number of overall hits +system.cpu.dcache.overall_hits::total 40380955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564863 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564863 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018485 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018485 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68573 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68573 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 579 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 579 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1583348 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583348 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651921 # number of overall misses +system.cpu.dcache.overall_misses::total 1651921 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9285321000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9285321000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14250906929 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14250906929 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5341000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5341000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23536227929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23536227929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23536227929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23536227929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128854 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128854 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15925 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904488 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904488 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033342 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033342 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025617 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025617 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051312 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051312 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532168 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532168 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037789 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037789 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039304 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039304 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9471.403813 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9471.403813 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14841.781919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14225.753143 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2896869 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131288 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.466667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.064995 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42032876 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42032876 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025613 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025613 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051309 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532234 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532234 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036356 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036356 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037785 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037785 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039301 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039301 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16438.182356 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16438.182356 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13992.260003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13992.260003 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9224.525043 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9224.525043 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14864.848365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14864.848365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14247.792678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14247.792678 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 81 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2899485 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131229 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.094849 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 485017 # number of writebacks -system.cpu.dcache.writebacks::total 485017 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265550 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 265550 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870019 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870019 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135569 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135569 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135569 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299413 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148529 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148529 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 485025 # number of writebacks +system.cpu.dcache.writebacks::total 485025 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265446 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 265446 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 869952 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 869952 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 579 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 579 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135398 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447942 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447942 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485539 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485539 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3625766000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3625766000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2305447971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2305447971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1884857000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1884857000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5931213971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5931213971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816070971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 447950 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447950 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485547 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485547 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3589129000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3589129000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306203970 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306203970 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1890576000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1890576000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5895332970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5895332970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7785908970 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7785908970 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291780 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291812 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11987.058183 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11987.058183 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15526.542721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15526.542721 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50285.288720 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50285.288720 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13160.694207 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13160.694207 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16035.335343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16035.335343 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 323105 # number of replacements -system.cpu.icache.tags.tagsinuse 510.281102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22444187 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323617 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.354166 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 323129 # number of replacements +system.cpu.icache.tags.tagsinuse 510.280955 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22445799 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323641 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.354003 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.281102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996643 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996643 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.280955 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996642 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996642 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 341 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 335 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45880575 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45880575 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22444187 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22444187 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22444187 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22444187 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22444187 # number of overall hits -system.cpu.icache.overall_hits::total 22444187 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334287 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334287 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334287 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334287 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334287 # number of overall misses -system.cpu.icache.overall_misses::total 334287 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3550514898 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3550514898 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3550514898 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3550514898 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3550514898 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3550514898 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22778474 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22778474 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22778474 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22778474 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22778474 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22778474 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10621.157562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10621.157562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10621.157562 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 261417 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45884745 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45884745 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22445799 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22445799 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22445799 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22445799 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22445799 # number of overall hits +system.cpu.icache.overall_hits::total 22445799 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334748 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334748 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334748 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334748 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334748 # number of overall misses +system.cpu.icache.overall_misses::total 334748 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3612917411 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3612917411 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3612917411 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3612917411 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3612917411 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3612917411 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22780547 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22780547 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22780547 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22780547 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22780547 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22780547 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014694 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014694 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014694 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014694 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014694 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014694 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10792.946966 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10792.946966 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10792.946966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10792.946966 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 264495 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16440 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16626 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.901277 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.908517 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 323105 # number of writebacks -system.cpu.icache.writebacks::total 323105 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10659 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 10659 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 10659 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 10659 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 10659 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 10659 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3274041434 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3274041434 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3274041434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3274041434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3274041434 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3274041434 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014208 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014208 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014208 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10116.681604 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10116.681604 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 323129 # number of writebacks +system.cpu.icache.writebacks::total 323129 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11096 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 11096 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 11096 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 11096 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 11096 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 11096 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323652 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323652 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323652 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323652 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323652 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323652 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3313255946 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3313255946 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3313255946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3313255946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3313255946 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3313255946 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014207 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014207 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014207 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10237.093996 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10237.093996 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 822385 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826178 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3328 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 821921 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 825508 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3147 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78886 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 128056 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15991.461548 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1186413 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 144416 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.215246 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78532 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 128137 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15990.250829 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1182553 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 144496 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.183984 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15890.954967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 100.506581 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.969907 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006134 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.976041 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 34 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15899.758864 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 90.491965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.970444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005523 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.975967 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 33 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 16326 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 18 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2702 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 578 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002075 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2752 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 551 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 772 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002014 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996460 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 24986640 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 24986640 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 253426 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 253426 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 474834 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 474834 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137075 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137075 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 312075 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 312075 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300547 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 300547 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 312075 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437622 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 749697 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 312075 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 437622 # number of overall hits -system.cpu.l2cache.overall_hits::total 749697 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 24991467 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 24991467 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 256728 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 256728 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 471596 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 471596 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137032 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137032 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 311398 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 311398 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300922 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 300922 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 311398 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 437954 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 749352 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 311398 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 437954 # number of overall hits +system.cpu.l2cache.overall_hits::total 749352 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11487 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11487 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 11542 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 11542 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36420 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 36420 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 11542 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 47907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 59449 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 11542 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 47907 # number of overall misses -system.cpu.l2cache.overall_misses::total 59449 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1187801500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1187801500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 872329000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 872329000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3000401500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3000401500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 872329000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4188203000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5060532000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 872329000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4188203000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5060532000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 253426 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 253426 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 474834 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 474834 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 11535 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11535 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12242 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 12242 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36048 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 36048 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 12242 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 47583 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 59825 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 12242 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 47583 # number of overall misses +system.cpu.l2cache.overall_misses::total 59825 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1188658000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1188658000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 916670500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 916670500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2966913000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2966913000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 916670500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4155571000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 5072241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 916670500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4155571000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 5072241500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 256728 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 256728 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 471596 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 471596 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148562 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148562 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323617 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 323617 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 336967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 323617 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485529 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 809146 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 323617 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485529 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 809146 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323640 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 323640 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336970 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 336970 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 323640 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 485537 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 809177 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 323640 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 485537 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 809177 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077321 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.077321 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.035666 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.035666 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.108082 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.108082 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.035666 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.098670 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.073471 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.035666 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.098670 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.073471 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103403.978410 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103403.978410 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75578.669208 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75578.669208 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82383.347062 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82383.347062 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75578.669208 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87423.612416 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85123.921344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75578.669208 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87423.612416 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85123.921344 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077642 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.077642 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.037826 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.037826 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.106977 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.106977 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.037826 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.098001 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.073933 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.037826 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.098001 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.073933 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103047.941049 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103047.941049 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74879.145564 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74879.145564 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82304.510652 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82304.510652 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84784.646887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84784.646887 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1071,156 +1067,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97338 # number of writebacks -system.cpu.l2cache.writebacks::total 97338 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3200 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3200 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 27 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 27 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 107 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 107 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3307 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3334 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3307 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3334 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112837 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 112837 # number of HardPFReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 97288 # number of writebacks +system.cpu.l2cache.writebacks::total 97288 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3173 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3173 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 34 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 34 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 93 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 93 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 34 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3266 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3300 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 34 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3266 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3300 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112494 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112494 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8287 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8287 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 11515 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 11515 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 36313 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 36313 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 11515 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 44600 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 56115 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 11515 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 44600 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112837 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168952 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10338050198 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 173000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 173000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 653811000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 653811000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 801316000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 801316000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2775072500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2775072500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801316000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3428883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4230199500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801316000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3428883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14568249698 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8362 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8362 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12208 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12208 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35955 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35955 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12208 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 44317 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 56525 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12208 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 44317 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112494 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169019 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10322993748 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 147000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 147000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 658062000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 658062000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 841432500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 841432500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2745124500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2745124500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 841432500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3403186500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4244619000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 841432500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3403186500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14567612748 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055781 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055781 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.035582 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.107764 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.107764 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056284 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056284 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037721 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.106701 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.106701 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069855 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208803 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208878 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91764.838551 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78696.723272 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78696.723272 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68924.680537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68924.680537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76348.894451 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76348.894451 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75092.773109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86189.202090 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1617289 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 808162 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79873 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67046 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10433 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 350764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 474834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 78545 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142478 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 1617353 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808194 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67170 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10592 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 354016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 551426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142034 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 939793 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2346582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39434560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 58959360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 98393920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318372 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1127528 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.139590 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.372305 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336970 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 970420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2426539 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41393152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62115968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103509120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318345 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1127532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.139813 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.372899 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 980569 86.97% 86.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136526 12.11% 99.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10433 0.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980480 86.96% 86.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136460 12.10% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10592 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1127528 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1616766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1127532 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616830500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485882115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485918614 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728582930 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728566986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 144336 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97338 # Transaction distribution -system.membus.trans_dist::CleanEvict 27827 # Transaction distribution +system.membus.trans_dist::ReadResp 144525 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97288 # Transaction distribution +system.membus.trans_dist::CleanEvict 27973 # Transaction distribution system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 8287 # Transaction distribution -system.membus.trans_dist::ReadExResp 8287 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144337 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 430432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 430432 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15997504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15997504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8362 # Transaction distribution +system.membus.trans_dist::ReadExResp 8362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144526 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 431046 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16011200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16011200 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 277799 # Request fanout histogram +system.membus.snoop_fanout::samples 278159 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 277799 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 278159 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 277799 # Request fanout histogram -system.membus.reqLayer0.occupancy 747949896 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 278159 # Request fanout histogram +system.membus.reqLayer0.occupancy 748401121 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 797228853 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 798557507 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |