diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/50.vortex/ref/arm/linux/o3-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing')
3 files changed, 311 insertions, 213 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 18c9a5809..1d9e3541a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,12 +508,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 08b53cf2f..e2d26e372 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:22 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 16:25:27 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index b5c5ac05d..228286404 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.031189 # Nu sim_ticks 31189496500 # Number of ticks simulated final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53036 # Simulator instruction rate (inst/s) -host_tick_rate 16437569 # Simulator tick rate (ticks/s) -host_mem_usage 264816 # Number of bytes of host memory used -host_seconds 1897.45 # Real time elapsed on the host -sim_insts 100634170 # Number of instructions simulated +host_inst_rate 144507 # Simulator instruction rate (inst/s) +host_op_rate 205068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63556485 # Simulator tick rate (ticks/s) +host_mem_usage 231932 # Number of bytes of host memory used +host_seconds 490.74 # Real time elapsed on the host +sim_insts 70914922 # Number of instructions simulated +sim_ops 100634170 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8651712 # Number of bytes read from this memory system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory system.physmem.bytes_written 5661248 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100639722 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 70920474 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100639722 # The number of committed instructions system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle -system.cpu.commit.count 100639722 # Number of instructions committed +system.cpu.commit.committedInsts 70920474 # Number of instructions committed +system.cpu.commit.committedOps 100639722 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 47865761 # Number of memory references committed system.cpu.commit.loads 27308566 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 166686934 # Th system.cpu.rob.rob_writes 227096473 # The number of ROB writes system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100634170 # Number of Instructions Simulated -system.cpu.committedInsts_total 100634170 # Number of Instructions Simulated -system.cpu.cpi 0.619859 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.619859 # CPI: Total CPI of All Threads -system.cpu.ipc 1.613270 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.613270 # IPC: Total IPC of All Threads +system.cpu.committedInsts 70914922 # Number of Instructions Simulated +system.cpu.committedOps 100634170 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70914922 # Number of Instructions Simulated +system.cpu.cpi 0.879631 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.879631 # CPI: Total CPI of All Threads +system.cpu.ipc 1.136840 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.136840 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 511674990 # number of integer regfile reads system.cpu.int_regfile_writes 103897673 # number of integer regfile writes system.cpu.fp_regfile_reads 166 # number of floating regfile reads @@ -336,26 +341,39 @@ system.cpu.icache.total_refs 12180358 # To system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1805.600642 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.881641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12180359 # number of ReadReq hits -system.cpu.icache.demand_hits 12180359 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12180359 # number of overall hits -system.cpu.icache.ReadReq_misses 29272 # number of ReadReq misses -system.cpu.icache.demand_misses 29272 # number of demand (read+write) misses -system.cpu.icache.overall_misses 29272 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 357988500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 357988500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 357988500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12209631 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12209631 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12209631 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002397 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002397 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002397 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12229.724652 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12229.724652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12229.724652 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1805.600642 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.881641 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.881641 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12180359 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12180359 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12180359 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12180359 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12180359 # number of overall hits +system.cpu.icache.overall_hits::total 12180359 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 29272 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 29272 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 29272 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 29272 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 29272 # number of overall misses +system.cpu.icache.overall_misses::total 29272 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 357988500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 357988500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 357988500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 357988500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 357988500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 357988500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12209631 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12209631 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12209631 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12209631 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12209631 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12209631 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002397 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002397 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002397 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12229.724652 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12229.724652 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,27 +382,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1063 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1063 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1063 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 28209 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 28209 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 28209 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 247071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 247071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 247071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8758.605410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8758.605410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8758.605410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1063 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1063 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1063 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1063 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1063 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1063 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28209 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28209 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28209 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28209 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28209 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28209 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 247071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 247071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 247071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 247071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 247071500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 247071500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8758.605410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8758.605410 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157892 # number of replacements system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use @@ -392,40 +415,63 @@ system.cpu.dcache.total_refs 44746410 # To system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4072.334227 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994222 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26399659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18310286 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 18924 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17376 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 44709945 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 44709945 # number of overall hits -system.cpu.dcache.ReadReq_misses 108879 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1539615 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 26 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1648494 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1648494 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2418798500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 52283607500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 349000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 54702406000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 54702406000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 26508538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 18950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17376 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46358439 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46358439 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004107 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035560 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035560 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22215.473140 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33958.884202 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13423.076923 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33183.260600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33183.260600 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4072.334227 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994222 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994222 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26399659 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26399659 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18310286 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18310286 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 18924 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18924 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 17376 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 17376 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44709945 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44709945 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44709945 # number of overall hits +system.cpu.dcache.overall_hits::total 44709945 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 108879 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 108879 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1539615 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1539615 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1648494 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1648494 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1648494 # number of overall misses +system.cpu.dcache.overall_misses::total 1648494 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2418798500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2418798500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52283607500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52283607500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 349000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 349000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54702406000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54702406000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54702406000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54702406000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26508538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26508538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18950 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 17376 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 17376 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46358439 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46358439 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46358439 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46358439 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004107 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077563 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035560 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035560 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22215.473140 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33958.884202 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.076923 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33183.260600 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,33 +480,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123473 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 53766 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1432695 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 26 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1486461 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1486461 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55113 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106920 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 28161 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 161984 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 190145 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.195093 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.493364 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.681818 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959685 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.195093 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.801129 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.195093 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.801129 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.367310 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34232.179001 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.626763 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,35 +607,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88457 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32586 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102597 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 135183 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 135183 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1012814500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 931000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197894500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4210709000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4210709000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391480 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.681818 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959685 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.710947 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.710947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.277236 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31033.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.473766 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 88457 # number of writebacks +system.cpu.l2cache.writebacks::total 88457 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27116 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 32586 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102597 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102597 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129713 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 135183 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5470 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129713 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 135183 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169929500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 842885000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1012814500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 931000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 931000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3197894500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3197894500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169929500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4040779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4210709000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169929500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4040779500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4210709000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.492329 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.681818 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959685 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |