diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:41 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:41 -0500 |
| commit | 91e74beee60b2085d18dfbfd51018dce2c779d8d (patch) | |
| tree | 96a71f2f316d24e9378bc3a68df207880e0eccca /tests/long/se/50.vortex/ref/arm/linux/o3-timing | |
| parent | 80a26a3e39874dab7c0b51cd5ce0258039494e30 (diff) | |
| download | gem5-91e74beee60b2085d18dfbfd51018dce2c779d8d.tar.xz | |
ARM: update stats for bp and squash fixes.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing')
3 files changed, 604 insertions, 597 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 0878a1dc0..b2095b317 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index c4aefb2c9..726190563 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:29:16 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:57:39 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24460150500 because target called exit() +Exiting @ tick 24260940500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bc1c3c499..fdf8f5a60 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024450 # Number of seconds simulated -sim_ticks 24450292500 # Number of ticks simulated -final_tick 24450292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024261 # Number of seconds simulated +sim_ticks 24260940500 # Number of ticks simulated +final_tick 24260940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166577 # Simulator instruction rate (inst/s) -host_op_rate 236377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57425524 # Simulator tick rate (ticks/s) -host_mem_usage 242552 # Number of bytes of host memory used -host_seconds 425.77 # Real time elapsed on the host -sim_insts 70924074 # Number of instructions simulated -sim_ops 100643321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 328512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8029568 # Number of bytes read from this memory -system.physmem.bytes_read::total 8358080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 328512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 328512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417984 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5133 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125462 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130595 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84656 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84656 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13435913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 328403760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 341839673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13435913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13435913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 221591787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 221591787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 221591787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13435913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 328403760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 563431460 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 115016 # Simulator instruction rate (inst/s) +host_op_rate 163211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39343372 # Simulator tick rate (ticks/s) +host_mem_usage 237732 # Number of bytes of host memory used +host_seconds 616.65 # Real time elapsed on the host +sim_insts 70924159 # Number of instructions simulated +sim_ops 100643406 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 327680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory +system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 327680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 327680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417600 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84650 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84650 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13506484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330903577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344410061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13506484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13506484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 223305440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 223305440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 223305440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13506484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330903577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 567715501 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48900586 # number of cpu cycles simulated +system.cpu.numCycles 48521882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16947895 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12979317 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 657239 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11568375 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7965689 # Number of BTB hits +system.cpu.BPredUnit.lookups 16966170 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12979168 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 675165 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11674119 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7996673 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1878366 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114401 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12822432 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87522774 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16947895 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9844055 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21770954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2772902 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11003856 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 471 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12059223 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 218909 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47624951 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336628 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1849293 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114426 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12701255 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 86893403 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16966170 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9845966 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21627617 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2635386 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10974011 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 407 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 11950097 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 196542 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47237958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.329156 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25875265 54.33% 54.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2171829 4.56% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2001256 4.20% 63.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2024856 4.25% 67.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1547627 3.25% 70.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1411228 2.96% 73.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 995461 2.09% 75.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1239299 2.60% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10358130 21.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25631712 54.26% 54.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2165185 4.58% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2027432 4.29% 63.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2093511 4.43% 67.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1492717 3.16% 70.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1413949 2.99% 73.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 984209 2.08% 75.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1226744 2.60% 78.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10202499 21.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47624951 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346579 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.789810 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15015037 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9311189 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19956662 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1421851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1920212 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3461414 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109087 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120161085 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 377153 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1920212 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16781785 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2961677 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 806772 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19529075 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5625430 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117632333 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12238 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4786667 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 232 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117758479 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541753123 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541746251 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6872 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99158984 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18599495 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37350 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37333 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13184553 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30073818 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22775187 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3642294 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4290989 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113312109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51967 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108452712 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 348423 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12547190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29979206 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14892 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47624951 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.277225 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996410 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47237958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349660 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.790809 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14870883 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9280138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19842641 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1415670 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1828626 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3426061 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108157 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118947297 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 370581 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1828626 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16604946 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2957626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 761420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19440844 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5644496 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116783060 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12596 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4803591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 254 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117118920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 537771429 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537766148 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5281 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17959800 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25743 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25726 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13145883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29944086 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22669898 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3682577 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4376453 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112886356 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41706 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108196580 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 320650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12119727 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28466628 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4614 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47237958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.991605 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11905380 25.00% 25.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8338489 17.51% 42.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7455711 15.66% 58.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7146400 15.01% 73.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5525482 11.60% 84.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3896676 8.18% 92.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1895621 3.98% 96.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 884969 1.86% 98.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 576223 1.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11517306 24.38% 24.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8382479 17.75% 42.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7488515 15.85% 57.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7167095 15.17% 73.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5452995 11.54% 84.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3887775 8.23% 92.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1886175 3.99% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 877063 1.86% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 578555 1.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47624951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47237958 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113237 4.46% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1413224 55.65% 60.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1012935 39.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 110786 4.40% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1390381 55.25% 59.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1015261 40.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57358153 52.89% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91504 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57217754 52.88% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91589 0.08% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 207 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 191 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued @@ -239,158 +239,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29210718 26.93% 79.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21792123 20.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29118364 26.91% 79.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21768675 20.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108452712 # Type of FU issued -system.cpu.iq.rate 2.217820 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2539396 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023415 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 267417480 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125938241 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106420258 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 714 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1140 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 175 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110991749 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 359 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2211393 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108196580 # Type of FU issued +system.cpu.iq.rate 2.229851 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2516428 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023258 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266467665 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125074926 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106294504 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 794 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110712739 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 269 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2177452 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2763421 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7106 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29349 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2216160 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2633672 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7610 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29131 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2110854 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1920212 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 926920 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38130 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113444221 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 341894 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30073818 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22775187 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35362 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2649 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29349 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 424803 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263892 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 688695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107241565 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28837233 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1211147 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1828626 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 932107 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 39617 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112937916 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 341621 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29944086 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22669898 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 25185 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2553 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3723 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29131 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 450221 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 202626 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 652847 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107016957 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28768203 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1179623 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80145 # number of nop insts executed -system.cpu.iew.exec_refs 50314250 # number of memory reference insts executed -system.cpu.iew.exec_branches 14661458 # Number of branches executed -system.cpu.iew.exec_stores 21477017 # Number of stores executed -system.cpu.iew.exec_rate 2.193053 # Inst execution rate -system.cpu.iew.wb_sent 106757510 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106420433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53411369 # num instructions producing a value -system.cpu.iew.wb_consumers 103767535 # num instructions consuming a value +system.cpu.iew.exec_nop 9854 # number of nop insts executed +system.cpu.iew.exec_refs 50224831 # number of memory reference insts executed +system.cpu.iew.exec_branches 14719282 # Number of branches executed +system.cpu.iew.exec_stores 21456628 # Number of stores executed +system.cpu.iew.exec_rate 2.205540 # Inst execution rate +system.cpu.iew.wb_sent 106535697 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106294668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53446146 # num instructions producing a value +system.cpu.iew.wb_consumers 103592779 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.176261 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514721 # average fanout of values written-back +system.cpu.iew.wb_rate 2.190654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.515925 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12796121 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37075 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612942 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45704740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.202154 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.735561 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12289679 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 569161 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45409333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.216482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.738259 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16269057 35.60% 35.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11908776 26.06% 61.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3615674 7.91% 69.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2919531 6.39% 75.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1872792 4.10% 80.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1908851 4.18% 84.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 687748 1.50% 85.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 590243 1.29% 87.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5932068 12.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15949772 35.12% 35.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11950425 26.32% 61.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3594230 7.92% 69.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2920439 6.43% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880725 4.14% 79.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1913412 4.21% 84.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 683428 1.51% 85.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 576988 1.27% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5939914 13.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45704740 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929626 # Number of instructions committed -system.cpu.commit.committedOps 100648873 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45409333 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929711 # Number of instructions committed +system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869424 # Number of memory references committed -system.cpu.commit.loads 27310397 # Number of loads committed +system.cpu.commit.refs 47869458 # Number of memory references committed +system.cpu.commit.loads 27310414 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671916 # Number of branches committed +system.cpu.commit.branches 13744811 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91485935 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5932068 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5939914 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153192367 # The number of ROB reads -system.cpu.rob.rob_writes 228820850 # The number of ROB writes -system.cpu.timesIdled 52344 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1275635 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924074 # Number of Instructions Simulated -system.cpu.committedOps 100643321 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924074 # Number of Instructions Simulated -system.cpu.cpi 0.689478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.689478 # CPI: Total CPI of All Threads -system.cpu.ipc 1.450373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.450373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516213591 # number of integer regfile reads -system.cpu.int_regfile_writes 104366681 # number of integer regfile writes -system.cpu.fp_regfile_reads 794 # number of floating regfile reads -system.cpu.fp_regfile_writes 662 # number of floating regfile writes -system.cpu.misc_regfile_reads 146023696 # number of misc regfile reads -system.cpu.misc_regfile_writes 38418 # number of misc regfile writes -system.cpu.icache.replacements 30034 # number of replacements -system.cpu.icache.tagsinuse 1814.104659 # Cycle average of tags in use -system.cpu.icache.total_refs 12025772 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32074 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 374.938330 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152382757 # The number of ROB reads +system.cpu.rob.rob_writes 227716793 # The number of ROB writes +system.cpu.timesIdled 52521 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1283924 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924159 # Number of Instructions Simulated +system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated +system.cpu.cpi 0.684138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.684138 # CPI: Total CPI of All Threads +system.cpu.ipc 1.461694 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.461694 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 515060291 # number of integer regfile reads +system.cpu.int_regfile_writes 104149739 # number of integer regfile writes +system.cpu.fp_regfile_reads 734 # number of floating regfile reads +system.cpu.fp_regfile_writes 618 # number of floating regfile writes +system.cpu.misc_regfile_reads 145340198 # number of misc regfile reads +system.cpu.misc_regfile_writes 38452 # number of misc regfile writes +system.cpu.icache.replacements 30556 # number of replacements +system.cpu.icache.tagsinuse 1813.467317 # Cycle average of tags in use +system.cpu.icache.total_refs 11916104 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32594 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 365.591949 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.104659 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885793 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885793 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12025773 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12025773 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12025773 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12025773 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12025773 # number of overall hits -system.cpu.icache.overall_hits::total 12025773 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33450 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33450 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33450 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33450 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33450 # number of overall misses -system.cpu.icache.overall_misses::total 33450 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 407167500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 407167500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 407167500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 407167500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 407167500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 407167500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12059223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12059223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12059223 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12059223 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12059223 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12059223 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002774 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002774 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002774 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002774 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002774 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002774 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12172.421525 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12172.421525 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12172.421525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12172.421525 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1813.467317 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885482 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885482 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11916104 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11916104 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11916104 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11916104 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11916104 # number of overall hits +system.cpu.icache.overall_hits::total 11916104 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33993 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33993 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33993 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33993 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33993 # number of overall misses +system.cpu.icache.overall_misses::total 33993 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409410000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409410000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409410000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409410000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409410000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409410000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11950097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11950097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11950097 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11950097 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11950097 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11950097 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002845 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002845 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002845 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002845 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002845 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002845 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12043.950225 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12043.950225 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12043.950225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12043.950225 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1320 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1320 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1320 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1320 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1320 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1320 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32130 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32130 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32130 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32130 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32130 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32130 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275291000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 275291000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275291000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 275291000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275291000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 275291000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002664 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002664 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002664 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8568.036103 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8568.036103 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1348 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1348 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1348 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1348 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1348 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1348 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32645 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8441.537755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8441.537755 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158627 # number of replacements -system.cpu.dcache.tagsinuse 4071.845451 # Cycle average of tags in use -system.cpu.dcache.total_refs 44602467 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162723 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.100570 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.845451 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994103 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994103 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 44571992 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162649 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.037910 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 270825000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.119478 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994170 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994170 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26246711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26246711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18285374 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18285374 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20492 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20492 # 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number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1671709 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1671709 # number of overall misses +system.cpu.dcache.overall_misses::total 1671709 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2591609000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2591609000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63424341000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63424341000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 645500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 645500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 66015950000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 66015950000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 66015950000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 66015950000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26353893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26353893 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20429 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20429 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19208 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19208 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46234184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46234184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46234184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46234184 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004052 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004052 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078820 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078820 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002007 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002007 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24192.212007 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24192.212007 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40524.306312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40524.306312 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14292.682927 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14292.682927 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39479.585927 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39479.585927 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20537 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20537 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46203794 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46203794 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46203794 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46203794 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078818 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078818 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002191 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002191 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036181 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036181 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036181 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036181 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24179.517083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24179.517083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40538.987822 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40538.987822 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14344.444444 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14344.444444 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39490.096662 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39490.096662 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 210000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 209500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19090.909091 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19045.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128131 # number of writebacks -system.cpu.dcache.writebacks::total 128131 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51186 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51186 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457528 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1457528 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1508714 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1508714 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1508714 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1508714 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55735 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55735 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107045 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107045 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162780 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162780 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162780 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162780 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 988383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3842536000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3842536000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4830919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4830919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4830919500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128129 # number of writebacks +system.cpu.dcache.writebacks::total 128129 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51511 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457497 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1457497 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1509008 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1509008 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1509008 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1509008 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55671 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55671 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162701 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162701 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162701 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162701 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 988702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3843974500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3843974500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4832676500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4832676500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4832676500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4832676500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17733.623396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17733.623396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35896.454762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35896.454762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17759.731278 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17759.731278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35914.925722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35914.925722 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 98022 # number of replacements -system.cpu.l2cache.tagsinuse 28617.589348 # Cycle average of tags in use -system.cpu.l2cache.total_refs 86966 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128812 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.675139 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 97977 # number of replacements +system.cpu.l2cache.tagsinuse 28615.045992 # Cycle average of tags in use +system.cpu.l2cache.total_refs 87467 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128770 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.679250 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25792.429972 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1163.052716 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1662.106660 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.787122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035494 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.050723 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.873340 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26908 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32482 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59390 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128131 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128131 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 37194 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 64102 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26908 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 37194 # number of overall hits -system.cpu.l2cache.overall_hits::total 64102 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5162 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 23218 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 28380 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 46 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 46 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102311 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102311 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5162 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125529 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130691 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5162 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 125529 # number of overall misses -system.cpu.l2cache.overall_misses::total 130691 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181399000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 833610000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1015009000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3562805000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3562805000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 181399000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4396415000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4577814000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 181399000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4396415000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4577814000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 32070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55700 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4005074000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4169215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164141000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4005074000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4169215000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320094 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.692308 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.692308 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.668712 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.668712 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32058.789062 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32795.415225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32661.862606 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31361.111111 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31361.111111 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31732.872026 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31732.872026 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |