diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/se/50.vortex/ref/arm/linux/o3-timing | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing')
3 files changed, 266 insertions, 262 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index fd73c9f26..be7e2dd7e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/gem5/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index dc0676551..ef0c59dbf 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 20:20:38 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 00:36:17 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 0ed850d63..3a52f894e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026292 # Nu sim_ticks 26292466000 # Number of ticks simulated final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139577 # Simulator instruction rate (inst/s) -host_op_rate 198063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51742306 # Simulator tick rate (ticks/s) -host_mem_usage 305460 # Number of bytes of host memory used -host_seconds 508.14 # Real time elapsed on the host +host_inst_rate 43892 # Simulator instruction rate (inst/s) +host_op_rate 62284 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16271073 # Simulator tick rate (ticks/s) +host_mem_usage 263196 # Number of bytes of host memory used +host_seconds 1615.90 # Real time elapsed on the host sim_insts 70925094 # Number of instructions simulated sim_ops 100644341 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 5127 # Tr system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26292446500 # Total gap between requests +system.physmem.totGap 26292447500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests +system.physmem.totQLat 4868163034 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests system.physmem.totBusLat 515096000 # Total cycles spent in databus access system.physmem.totBankLat 1373176000 # Total cycles spent in bank access -system.physmem.avgQLat 37803.91 # Average queueing delay per request +system.physmem.avgQLat 37803.93 # Average queueing delay per request system.physmem.avgBankLat 10663.46 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52467.37 # Average memory access latency +system.physmem.avgMemAccLat 52467.38 # Average memory access latency system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s @@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 7769778 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) @@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing @@ -289,20 +289,20 @@ system.cpu.decode.SquashedInsts 360894 # Nu system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running +system.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19086496 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer @@ -317,11 +317,11 @@ system.cpu.iq.iqSquashedInstsIssued 269260 # Nu system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle @@ -333,7 +333,7 @@ system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available @@ -406,7 +406,7 @@ system.cpu.iq.FU_type_0::total 107204361 # Ty system.cpu.iq.rate 2.038690 # Inst issue rate system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads @@ -429,7 +429,7 @@ system.cpu.iew.iewSquashCycles 1617500 # Nu system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions @@ -459,11 +459,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle @@ -475,7 +475,7 @@ system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle system.cpu.commit.committedInsts 70930646 # Number of instructions committed system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -488,10 +488,10 @@ system.cpu.commit.int_insts 91486751 # Nu system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149890854 # The number of ROB reads +system.cpu.rob.rob_reads 149890856 # The number of ROB reads system.cpu.rob.rob_writes 224611140 # The number of ROB writes system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70925094 # Number of Instructions Simulated system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated @@ -506,12 +506,12 @@ system.cpu.fp_regfile_writes 582 # nu system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads system.cpu.misc_regfile_writes 38826 # number of misc regfile writes system.cpu.icache.replacements 30543 # number of replacements -system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits @@ -520,36 +520,36 @@ system.cpu.icache.demand_hits::cpu.inst 11635567 # nu system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits system.cpu.icache.overall_hits::total 11635567 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses -system.cpu.icache.overall_misses::total 36657 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses +system.cpu.icache.overall_misses::total 36658 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 709083999 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked @@ -558,172 +558,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3773 # 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mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158306 # number of replacements -system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use -system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits -system.cpu.dcache.overall_hits::total 44303188 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks -system.cpu.dcache.writebacks::total 129052 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 95650 # number of replacements -system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy @@ -756,19 +630,19 @@ system.cpu.l2cache.demand_misses::total 128851 # nu system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses system.cpu.l2cache.overall_misses::total 128851 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269870000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664898500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1934768500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269871000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664900000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1934771000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8091962000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 8091962000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 269870000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9756860500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10026730500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 269870000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9756860500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10026730500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 269871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9756862000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10026733000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9756862000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10026733000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 32373 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55368 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 87741 # number of ReadReq accesses(hits+misses) @@ -797,19 +671,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.661538 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144565 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.764590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.661538 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.529915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.727812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.332581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.743590 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.796258 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.426584 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 77.181208 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 77.181208 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79134.349085 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79134.349085 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77816.474067 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77816.474067 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77816.493469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77816.493469 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -842,19 +716,19 @@ system.cpu.l2cache.demand_mshr_misses::total 128777 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124113 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210181444 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210183444 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1389842080 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600023524 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600025524 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2980298 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2980298 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6821241683 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6821241683 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210181444 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210183444 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8211083763 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8421267207 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210183444 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses @@ -868,19 +742,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 158306 # number of replacements +system.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use +system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits +system.cpu.dcache.overall_hits::total 44303188 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses +system.cpu.dcache.overall_misses::total 1709363 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks +system.cpu.dcache.writebacks::total 129052 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |