diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/50.vortex/ref/arm/linux/o3-timing | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing')
3 files changed, 621 insertions, 625 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 566c57286..33fd8bc7c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index cb33c4c0f..462a53b1f 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:32:39 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:13:16 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24560764000 because target called exit() +Exiting @ tick 23981004500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 826f949e8..8d4101747 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024561 # Number of seconds simulated -sim_ticks 24560764000 # Number of ticks simulated -final_tick 24560764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023981 # Number of seconds simulated +sim_ticks 23981004500 # Number of ticks simulated +final_tick 23981004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104807 # Simulator instruction rate (inst/s) -host_op_rate 148726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36296181 # Simulator tick rate (ticks/s) -host_mem_usage 240672 # Number of bytes of host memory used -host_seconds 676.68 # Real time elapsed on the host -sim_insts 70920072 # Number of instructions simulated -sim_ops 100639320 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 367552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8319680 # Number of bytes read from this memory -system.physmem.bytes_read::total 8687232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5661632 # Number of bytes written to this memory -system.physmem.bytes_written::total 5661632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 129995 # Number of read requests responded to by this memory -system.physmem.num_reads::total 135738 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88463 # Number of write requests responded to by this memory -system.physmem.num_writes::total 88463 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 14965007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 338738648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 353703655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 14965007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 14965007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 230515305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 230515305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 230515305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 14965007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 338738648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 584218960 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 169152 # Simulator instruction rate (inst/s) +host_op_rate 240031 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57193739 # Simulator tick rate (ticks/s) +host_mem_usage 242580 # Number of bytes of host memory used +host_seconds 419.29 # Real time elapsed on the host +sim_insts 70924419 # Number of instructions simulated +sim_ops 100643666 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8029184 # Number of bytes read from this memory +system.physmem.bytes_read::total 8356160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417856 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130565 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84654 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84654 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13634792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 334814332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 348449124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13634792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13634792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 225922813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 225922813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 225922813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13634792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 334814332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 574371937 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 49121529 # number of cpu cycles simulated +system.cpu.numCycles 47962010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17484643 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13346532 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 763895 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12042742 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8272877 # Number of BTB hits +system.cpu.BPredUnit.lookups 16947214 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12982117 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 655322 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11804628 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7961599 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1873235 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 186435 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13233353 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 89314081 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17484643 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10146112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22235900 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3054378 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9993886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 494 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12432222 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 242141 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47666513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.625620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.342151 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1880669 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114490 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12764738 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87540471 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16947214 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9842268 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21772804 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2768546 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10027678 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12061426 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218802 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46590944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.639937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.350838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25452916 53.40% 53.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2276272 4.78% 58.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2010669 4.22% 62.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2082167 4.37% 66.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1606372 3.37% 70.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1473384 3.09% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1003270 2.10% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1293693 2.71% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10467770 21.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24839551 53.31% 53.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2175787 4.67% 57.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1999394 4.29% 62.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2026993 4.35% 66.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1551688 3.33% 69.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1408138 3.02% 72.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 990048 2.12% 75.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1240896 2.66% 77.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10358449 22.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47666513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355947 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.818227 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15402794 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8395926 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20419082 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1357324 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2091387 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3552582 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 114889 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122010152 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 381349 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2091387 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17235553 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2381046 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 774700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19895179 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5288648 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 118965286 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 65 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 10051 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4471697 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 173 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 119289544 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 547314245 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 547305502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8743 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99152581 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20136963 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50089 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 50062 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12897670 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30342934 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22764283 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3373932 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4070444 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 114201865 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 59946 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108885427 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 355885 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13447173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32642565 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23673 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47666513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.284317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003120 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 46590944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.353347 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.825204 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14883106 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8408681 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19993372 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1386692 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1919093 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3458129 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108409 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120163882 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 373498 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1919093 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16645469 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2316120 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 802815 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19569476 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5337971 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117636894 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4512387 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 221 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117778889 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541771281 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541766916 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4365 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159536 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18619353 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37368 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37363 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12895568 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30067923 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22776958 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3590168 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4248242 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113315749 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51911 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108455143 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 350648 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12554662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29999283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14767 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46590944 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.327816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.997244 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11902735 24.97% 24.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8314690 17.44% 42.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7496951 15.73% 58.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072171 14.84% 72.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5553695 11.65% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3902484 8.19% 92.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1926147 4.04% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 904880 1.90% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 592760 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11127507 23.88% 23.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8067707 17.32% 41.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7375197 15.83% 57.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7162683 15.37% 72.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5557871 11.93% 84.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3930157 8.44% 92.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1905355 4.09% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881142 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 583325 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47666513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46590944 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112261 4.35% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1423319 55.12% 59.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1046695 40.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112830 4.40% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1425910 55.61% 60.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1025351 39.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57627292 52.92% 52.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 88925 0.08% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 277 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29380371 26.98% 79.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21788555 20.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57362458 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91498 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 129 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29209051 26.93% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21792000 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108885427 # Type of FU issued -system.cpu.iq.rate 2.216654 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2582277 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023716 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 268374678 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127734912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106613834 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 851 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 211 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111467277 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 427 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2219770 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108455143 # Type of FU issued +system.cpu.iq.rate 2.261272 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2564091 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023642 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266415556 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125949072 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106420629 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 111019028 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 206 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2223683 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3033338 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8348 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28761 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2206058 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2757457 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7931 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28755 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2217862 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 51 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2091387 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 991755 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 114342127 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 442332 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30342934 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22764283 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 43712 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1891 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1967 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28761 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 532244 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 266639 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 798883 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107583415 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28980389 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1302012 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1919093 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 944512 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 30820 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113447794 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342667 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30067923 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22776958 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35363 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28755 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 424789 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263529 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 688318 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107242187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28840669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1212956 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80316 # number of nop insts executed -system.cpu.iew.exec_refs 50461236 # number of memory reference insts executed -system.cpu.iew.exec_branches 14752818 # Number of branches executed -system.cpu.iew.exec_stores 21480847 # Number of stores executed -system.cpu.iew.exec_rate 2.190148 # Inst execution rate -system.cpu.iew.wb_sent 106971474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106614045 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53628736 # num instructions producing a value -system.cpu.iew.wb_consumers 104822222 # num instructions consuming a value +system.cpu.iew.exec_nop 80134 # number of nop insts executed +system.cpu.iew.exec_refs 50312690 # number of memory reference insts executed +system.cpu.iew.exec_branches 14662886 # Number of branches executed +system.cpu.iew.exec_stores 21472021 # Number of stores executed +system.cpu.iew.exec_rate 2.235982 # Inst execution rate +system.cpu.iew.wb_sent 106754958 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106420762 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53610539 # num instructions producing a value +system.cpu.iew.wb_consumers 104702454 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.170414 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511616 # average fanout of values written-back +system.cpu.iew.wb_rate 2.218855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512028 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70925624 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100644872 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 13697900 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 36273 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 715054 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45575127 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.208329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.734720 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70929971 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100649218 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12799085 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37144 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 611847 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44671852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.253079 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.750865 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16228357 35.61% 35.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11797211 25.89% 61.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3508330 7.70% 69.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2972714 6.52% 75.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1972056 4.33% 80.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1932722 4.24% 84.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 698627 1.53% 85.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 551617 1.21% 87.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5913493 12.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15424353 34.53% 34.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724908 26.25% 60.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3540913 7.93% 68.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2916552 6.53% 75.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1906207 4.27% 79.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1948042 4.36% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 684228 1.53% 85.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 590770 1.32% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5935879 13.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45575127 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70925624 # Number of instructions committed -system.cpu.commit.committedOps 100644872 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44671852 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929971 # Number of instructions committed +system.cpu.commit.committedOps 100649218 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47867821 # Number of memory references committed -system.cpu.commit.loads 27309596 # Number of loads committed +system.cpu.commit.refs 47869562 # Number of memory references committed +system.cpu.commit.loads 27310466 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671115 # Number of branches committed +system.cpu.commit.branches 13671985 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91482735 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486211 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5913493 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5935879 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153979107 # The number of ROB reads -system.cpu.rob.rob_writes 230788170 # The number of ROB writes -system.cpu.timesIdled 64143 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1455016 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70920072 # Number of Instructions Simulated -system.cpu.committedOps 100639320 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70920072 # Number of Instructions Simulated -system.cpu.cpi 0.692632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692632 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443768 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443768 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 517371049 # number of integer regfile reads -system.cpu.int_regfile_writes 104514948 # number of integer regfile writes -system.cpu.fp_regfile_reads 1051 # number of floating regfile reads -system.cpu.fp_regfile_writes 886 # number of floating regfile writes -system.cpu.misc_regfile_reads 147913903 # number of misc regfile reads -system.cpu.misc_regfile_writes 36814 # number of misc regfile writes -system.cpu.icache.replacements 31518 # number of replacements -system.cpu.icache.tagsinuse 1822.469235 # Cycle average of tags in use -system.cpu.icache.total_refs 12397113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 33561 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 369.390453 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152158977 # The number of ROB reads +system.cpu.rob.rob_writes 228826081 # The number of ROB writes +system.cpu.timesIdled 61655 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1371066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924419 # Number of Instructions Simulated +system.cpu.committedOps 100643666 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924419 # Number of Instructions Simulated +system.cpu.cpi 0.676241 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.676241 # CPI: Total CPI of All Threads +system.cpu.ipc 1.478762 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.478762 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516206868 # number of integer regfile reads +system.cpu.int_regfile_writes 104370444 # number of integer regfile writes +system.cpu.fp_regfile_reads 520 # number of floating regfile reads +system.cpu.fp_regfile_writes 444 # number of floating regfile writes +system.cpu.misc_regfile_reads 146052754 # number of misc regfile reads +system.cpu.misc_regfile_writes 38556 # number of misc regfile writes +system.cpu.icache.replacements 29824 # number of replacements +system.cpu.icache.tagsinuse 1820.810833 # Cycle average of tags in use +system.cpu.icache.total_refs 12028408 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 31867 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 377.456554 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1822.469235 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889878 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889878 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12397114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12397114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12397114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12397114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12397114 # number of overall hits -system.cpu.icache.overall_hits::total 12397114 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35108 # number of overall misses -system.cpu.icache.overall_misses::total 35108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406151000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406151000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406151000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406151000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406151000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406151000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12432222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12432222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12432222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12432222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12432222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12432222 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002824 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002824 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002824 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002824 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002824 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002824 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11568.616839 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11568.616839 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1820.810833 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.889068 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.889068 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12028408 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12028408 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12028408 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12028408 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12028408 # number of overall hits +system.cpu.icache.overall_hits::total 12028408 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33018 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33018 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33018 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33018 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33018 # number of overall misses +system.cpu.icache.overall_misses::total 33018 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 367424500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 367424500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 367424500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 367424500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 367424500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 367424500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12061426 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12061426 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12061426 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12061426 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12061426 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12061426 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11128.005936 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11128.005936 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11128.005936 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11128.005936 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,258 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1474 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1474 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1474 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1474 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1474 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1474 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33634 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33634 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33634 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33634 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33634 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33634 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268782500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 268782500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268782500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 268782500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268782500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 268782500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002705 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002705 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002705 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002705 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7991.392638 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7991.392638 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7991.392638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7991.392638 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1111 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1111 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1111 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1111 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1111 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31907 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31907 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31907 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244055000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 244055000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244055000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 244055000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244055000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 244055000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002645 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002645 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002645 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7648.948507 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7648.948507 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158907 # number of replacements -system.cpu.dcache.tagsinuse 4070.754102 # Cycle average of tags in use -system.cpu.dcache.total_refs 44741379 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 163003 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.481936 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4070.754102 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.993836 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.993836 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26393302 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26393302 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18309799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18309799 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 19644 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 19644 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 18406 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 18406 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44703101 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44703101 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44703101 # number of overall hits -system.cpu.dcache.overall_hits::total 44703101 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 110193 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 110193 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1540102 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1540102 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1650295 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1650295 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1650295 # number of overall misses -system.cpu.dcache.overall_misses::total 1650295 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2434975500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2434975500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52525381000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52525381000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 425000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 425000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54960356500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54960356500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54960356500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54960356500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26503495 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26503495 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158597 # number of replacements +system.cpu.dcache.tagsinuse 4071.944277 # Cycle average of tags in use +system.cpu.dcache.total_refs 44611539 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162693 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.206874 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 262057000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4071.944277 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994127 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994127 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26269994 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26269994 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18301608 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18301608 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20534 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20534 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19277 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19277 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44571602 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44571602 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44571602 # number of overall hits +system.cpu.dcache.overall_hits::total 44571602 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 105369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 105369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1548293 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1548293 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1653662 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1653662 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1653662 # number of overall misses +system.cpu.dcache.overall_misses::total 1653662 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2114831500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2114831500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52578719498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52578719498 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 447000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54693550998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54693550998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54693550998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54693550998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26375363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26375363 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19679 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 19679 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 18406 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 18406 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46353396 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46353396 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46353396 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46353396 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004158 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077587 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.077587 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001779 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001779 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035602 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035602 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33303.352734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33303.352734 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20573 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20573 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19277 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19277 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46225264 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46225264 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46225264 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46225264 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003995 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003995 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078000 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078000 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001896 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001896 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20070.718143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20070.718143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33959.153402 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33959.153402 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11461.538462 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11461.538462 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33074.201982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33074.201982 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 203500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123795 # number of writebacks -system.cpu.dcache.writebacks::total 123795 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54073 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54073 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1433145 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1433145 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1487218 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1487218 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1487218 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1487218 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56120 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56120 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106957 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106957 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 163077 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 163077 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 163077 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 163077 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1049489500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1049489500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3666942000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3666942000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4716431500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4716431500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4716431500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4716431500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 128124 # number of writebacks +system.cpu.dcache.writebacks::total 128124 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49671 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49671 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1441258 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1441258 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1490929 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1490929 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1490929 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1490929 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55698 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55698 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162733 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162733 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162733 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162733 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 907626500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 907626500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3661924998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3661924998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4569551498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4569551498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4569551498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4569551498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16295.495350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16295.495350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34212.407138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34212.407138 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115487 # number of replacements -system.cpu.l2cache.tagsinuse 18346.494934 # Cycle average of tags in use -system.cpu.l2cache.total_refs 78611 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 134352 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.585112 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 97993 # number of replacements +system.cpu.l2cache.tagsinuse 28658.689941 # Cycle average of tags in use +system.cpu.l2cache.total_refs 86749 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128784 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.673601 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15851.533035 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 880.199051 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1614.762848 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.483750 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.026862 # 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number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102314 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102314 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5109 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130565 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5109 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130565 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158798500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 719908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 878707000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1150000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1150000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3191239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3191239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158798500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3911148000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4069946500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158798500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3911148000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4069946500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.322780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.925000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.925000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.671096 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.671096 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.110002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31108.309567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31103.571555 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31190.643509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31190.643509 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |