Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.

1 files changed, 7 insertions, 7 deletions

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 3a7d388e3..fe9fd6111 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.023747                       # Nu
 sim_ticks                                 23747395500                       # Number of ticks simulated
 final_tick                                23747395500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107822                       # Simulator instruction rate (inst/s)
-host_op_rate                                   153002                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               36101670                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242616                       # Number of bytes of host memory used
-host_seconds                                   657.79                       # Real time elapsed on the host
+host_inst_rate                                 142184                       # Simulator instruction rate (inst/s)
+host_op_rate                                   201762                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47606944                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237384                       # Number of bytes of host memory used
+host_seconds                                   498.82                       # Real time elapsed on the host
 sim_insts                                    70924309                       # Number of instructions simulated
 sim_ops                                     100643556                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            325888                       # Number of bytes read from this memory
@@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33713.205595
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 33713.205595                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       197000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          394                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              10                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        19700                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    39.400000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       128103                       # number of writebacks