diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt | |
parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt')
-rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt | 45 |
1 files changed, 40 insertions, 5 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 987b2c223..d5f8b245c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1050888 # Simulator instruction rate (inst/s) -host_op_rate 1491308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 799239680 # Simulator tick rate (ticks/s) -host_mem_usage 322556 # Number of bytes of host memory used -host_seconds 67.48 # Real time elapsed on the host +host_inst_rate 1371353 # Simulator instruction rate (inst/s) +host_op_rate 1946078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1042965622 # Simulator tick rate (ticks/s) +host_mem_usage 308436 # Number of bytes of host memory used +host_seconds 51.71 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 107864315 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction +system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 100634375 # Class of executed instruction ---------- End Simulation Statistics ---------- |