diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/se/50.vortex/ref/arm/linux | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux')
10 files changed, 1212 insertions, 887 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 3a6f7de14..20429e4aa 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index 1a4f96712..78695e4f1 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1 +1,2 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 51d96dffd..0fe32cbd7 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:17:11 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:54:40 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5a6c340 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 26810051000 because target called exit() +Exiting @ tick 26790388000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 044953ad0..9978094b9 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026810 # Number of seconds simulated -sim_ticks 26810051000 # Number of ticks simulated -final_tick 26810051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026790 # Number of seconds simulated +sim_ticks 26790388000 # Number of ticks simulated +final_tick 26790388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140336 # Simulator instruction rate (inst/s) -host_op_rate 199155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53060871 # Simulator tick rate (ticks/s) -host_mem_usage 257660 # Number of bytes of host memory used -host_seconds 505.27 # Real time elapsed on the host +host_inst_rate 134448 # Simulator instruction rate (inst/s) +host_op_rate 190799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50797444 # Simulator tick rate (ticks/s) +host_mem_usage 278572 # Number of bytes of host memory used +host_seconds 527.40 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 299136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 299136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 299136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4674 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128787 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11157607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296278138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307435745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11157607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11157607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200395292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200395292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200395292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11157607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296278138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 507831037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128788 # Number of read requests accepted -system.physmem.writeReqs 83947 # Number of write requests accepted -system.physmem.readBursts 128788 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83947 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8242304 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 297344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942912 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5371968 # Number of bytes written to this memory +system.physmem.bytes_written::total 5371968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124108 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128754 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83937 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83937 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11098906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296483649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307582555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11098906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11098906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200518484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200518484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200518484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11098906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296483649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508101040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128754 # Number of read requests accepted +system.physmem.writeReqs 83937 # Number of write requests accepted +system.physmem.readBursts 128754 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83937 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8240128 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8242432 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372608 # Total written bytes from the system interface side +system.physmem.bytesWritten 5371648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8240256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5371968 # Total written bytes from the system interface side system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8141 # Per bank write bursts -system.physmem.perBankRdBursts::1 8391 # Per bank write bursts -system.physmem.perBankRdBursts::2 8249 # Per bank write bursts -system.physmem.perBankRdBursts::3 8162 # Per bank write bursts -system.physmem.perBankRdBursts::4 8307 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts +system.physmem.perBankRdBursts::0 8131 # Per bank write bursts +system.physmem.perBankRdBursts::1 8390 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts +system.physmem.perBankRdBursts::3 8163 # Per bank write bursts +system.physmem.perBankRdBursts::4 8302 # Per bank write bursts +system.physmem.perBankRdBursts::5 8446 # Per bank write bursts system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7966 # Per bank write bursts +system.physmem.perBankRdBursts::7 7962 # Per bank write bursts system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7616 # Per bank write bursts -system.physmem.perBankRdBursts::10 7784 # Per bank write bursts -system.physmem.perBankRdBursts::11 7815 # Per bank write bursts -system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7887 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8012 # Per bank write bursts -system.physmem.perBankWrBursts::0 5178 # Per bank write bursts +system.physmem.perBankRdBursts::9 7613 # Per bank write bursts +system.physmem.perBankRdBursts::10 7786 # Per bank write bursts +system.physmem.perBankRdBursts::11 7812 # Per bank write bursts +system.physmem.perBankRdBursts::12 7879 # Per bank write bursts +system.physmem.perBankRdBursts::13 7885 # Per bank write bursts +system.physmem.perBankRdBursts::14 7978 # Per bank write bursts +system.physmem.perBankRdBursts::15 8010 # Per bank write bursts +system.physmem.perBankWrBursts::0 5179 # Per bank write bursts system.physmem.perBankWrBursts::1 5375 # Per bank write bursts -system.physmem.perBankWrBursts::2 5292 # Per bank write bursts +system.physmem.perBankWrBursts::2 5289 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5267 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5206 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5028 # Per bank write bursts -system.physmem.perBankWrBursts::9 5090 # Per bank write bursts -system.physmem.perBankWrBursts::10 5248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5142 # Per bank write bursts +system.physmem.perBankWrBursts::6 5207 # Per bank write bursts +system.physmem.perBankWrBursts::7 5048 # Per bank write bursts +system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::9 5089 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5144 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5222 # Per bank write bursts +system.physmem.perBankWrBursts::15 5226 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26810034000 # Total gap between requests +system.physmem.totGap 26790282500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128788 # Read request sizes (log2) +system.physmem.readPktSize::6 128754 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83947 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 72914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83937 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,31 +129,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -161,190 +161,208 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 358.604352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.758574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 692.410978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15190 40.02% 40.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5700 15.02% 55.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3416 9.00% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2313 6.09% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1704 4.49% 74.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1539 4.05% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1108 2.92% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 903 2.38% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 681 1.79% 85.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 548 1.44% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 355 0.94% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 578 1.52% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 299 0.79% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 386 1.02% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 183 0.48% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 223 0.59% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 117 0.31% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 252 0.66% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 118 0.31% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 257 0.68% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 108 0.28% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 421 1.11% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 88 0.23% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 246 0.65% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 122 0.32% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 43 0.11% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 88 0.23% 97.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 65 0.17% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 27 0.07% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 45 0.12% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 16 0.04% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 15 0.04% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 29 0.08% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 15 0.04% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.276222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.215706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 692.456870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15075 39.80% 39.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5750 15.18% 54.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3421 9.03% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2320 6.12% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1668 4.40% 74.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1547 4.08% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1100 2.90% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 895 2.36% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 687 1.81% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 539 1.42% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 385 1.02% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 594 1.57% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 272 0.72% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 354 0.93% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 173 0.46% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 239 0.63% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 118 0.31% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 108 0.29% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 279 0.74% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 118 0.31% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 446 1.18% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 106 0.28% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 237 0.63% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 118 0.31% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 42 0.11% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 85 0.22% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 20 0.05% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 62 0.16% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 44 0.12% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 19 0.05% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 33 0.09% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 16 0.04% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 33 0.09% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 34 0.09% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 13 0.03% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 17 0.04% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 7 0.02% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 19 0.05% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 33 0.09% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 14 0.04% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 23 0.06% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 10 0.03% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 17 0.04% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 10 0.03% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 27 0.07% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 7 0.02% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 14 0.04% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.03% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 15 0.04% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 11 0.03% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 10 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 18 0.05% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 17 0.04% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.03% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.05% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 26 0.07% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 4 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 10 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 5 0.01% 98.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 13 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 8 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 13 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 9 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 8 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 7 0.02% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 6 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 9 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 7 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 16 0.04% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 9 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 10 0.03% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 10 0.03% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 7 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 6 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 7 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 6 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 7 0.02% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 7 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 5 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.01% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 2 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 6 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 6 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 3 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 5 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 35 0.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37958 # Bytes accessed per row activation -system.physmem.totQLat 3020745250 # Total ticks spent queuing -system.physmem.totMemAccLat 4967419000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643930000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1302743750 # Total ticks spent accessing banks -system.physmem.avgQLat 23455.54 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10115.57 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::6464-6465 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 4 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 6 0.02% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 37 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37879 # Bytes accessed per row activation +system.physmem.totQLat 3022726750 # Total ticks spent queuing +system.physmem.totMemAccLat 4971045500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643760000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1304558750 # Total ticks spent accessing banks +system.physmem.avgQLat 23477.12 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10132.34 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38571.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38609.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.73 # Average write queue length when enqueuing -system.physmem.readRowHits 117878 # Number of row buffer hits during reads -system.physmem.writeRowHits 56878 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.75 # Row buffer hit rate for writes -system.physmem.avgGap 126025.50 # Average gap between requests -system.physmem.pageHitRate 82.15 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 507831037 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26531 # Transaction distribution -system.membus.trans_dist::ReadResp 26530 # Transaction distribution -system.membus.trans_dist::Writeback 83947 # Transaction distribution +system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing +system.physmem.readRowHits 117872 # Number of row buffer hits during reads +system.physmem.writeRowHits 56933 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.83 # Row buffer hit rate for writes +system.physmem.avgGap 125958.70 # Average gap between requests +system.physmem.pageHitRate 82.19 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.78 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 508101040 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26500 # Transaction distribution +system.membus.trans_dist::ReadResp 26500 # Transaction distribution +system.membus.trans_dist::Writeback 83937 # Transaction distribution system.membus.trans_dist::UpgradeReq 308 # Transaction distribution system.membus.trans_dist::UpgradeResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 102257 # Transaction distribution -system.membus.trans_dist::ReadExResp 102257 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342138 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13614976 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13614976 # Total data (bytes) +system.membus.trans_dist::ReadExReq 102254 # Transaction distribution +system.membus.trans_dist::ReadExResp 102254 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13612224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13612224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13612224 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934752500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934459500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203686693 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203485442 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16646392 # Number of BP lookups -system.cpu.branchPred.condPredicted 12773976 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 607235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10818826 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7781096 # Number of BTB hits +system.cpu.branchPred.lookups 16615535 # Number of BP lookups +system.cpu.branchPred.condPredicted 12754556 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602333 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10795457 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7770077 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.921815 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825486 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113411 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.975434 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823925 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112966 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -366,6 +384,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -388,239 +427,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53620103 # number of cpu cycles simulated +system.cpu.numCycles 53580777 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12555863 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85327612 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16646392 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9606582 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21220606 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2386309 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10655499 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 479 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11697004 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 183631 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46184612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.586702 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12546836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85170403 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16615535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9594002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21183792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2362024 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10685029 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 557 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11675856 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333163 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24984951 54.10% 54.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138585 4.63% 58.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1966197 4.26% 62.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2046003 4.43% 67.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1469884 3.18% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1382868 2.99% 73.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958032 2.07% 75.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1189943 2.58% 78.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10048149 21.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24986446 54.14% 54.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137638 4.63% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1962079 4.25% 63.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2043997 4.43% 67.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466310 3.18% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1377582 2.99% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 960310 2.08% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1185958 2.57% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10029003 21.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46184612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310451 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.591336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14642918 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9005955 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19517473 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1369283 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1648983 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334820 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105179 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116999070 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363013 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1648983 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16350179 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2575616 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1030832 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19130431 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5448571 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115098604 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17023 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4589680 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115425064 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 530260724 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476967295 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2691 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310103 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.589570 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14635353 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9029918 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19485051 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1368887 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1630114 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3325603 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104819 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116788167 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1630114 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16340014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2585458 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1028005 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19100045 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5465687 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114914880 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17272 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4606354 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 316 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115243032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529540867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476170049 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2600 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16292392 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16110360 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12970121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29626660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22464166 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3855353 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4357218 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111639066 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36000 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107318490 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 273494 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10897204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26020912 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46184612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.323685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.992080 # Number of insts issued each cycle +system.cpu.rename.skidInsts 12995984 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29602749 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22439249 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3932152 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4401403 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111507434 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36062 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107242523 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272405 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10768427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25739903 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46149323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.323816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990206 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10954733 23.72% 23.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8081116 17.50% 41.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7387326 16.00% 57.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7126917 15.43% 72.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408207 11.71% 84.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3931545 8.51% 92.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1847862 4.00% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 871002 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 575904 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10919279 23.66% 23.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8079518 17.51% 41.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7423472 16.09% 57.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7094481 15.37% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5420902 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3930329 8.52% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1841974 3.99% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869423 1.88% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 569945 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46184612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46149323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112087 4.51% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 3 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1355242 54.58% 59.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1015813 40.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112279 4.53% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1361817 54.98% 59.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1002641 40.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56685703 52.82% 52.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91410 0.09% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 203 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28899327 26.93% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21641840 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56635396 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91455 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 208 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28883502 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21631955 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107318490 # Type of FU issued -system.cpu.iq.rate 2.001460 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2483145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023138 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263577666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122600736 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105627540 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 565 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 906 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109801353 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2178214 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107242523 # Type of FU issued +system.cpu.iq.rate 2.001511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2476739 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023095 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263382945 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122340040 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105564996 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 568 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 856 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109718975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 287 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181751 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2319552 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6675 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1908428 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2295641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6455 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29983 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1883511 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 694 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 679 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1648983 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1092293 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45577 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111684840 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 295051 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29626660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22464166 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20080 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6356 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5380 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 395595 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 182079 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 577674 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106281813 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28597262 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1036677 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1630114 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1093825 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45147 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111553302 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29602749 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22439249 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20142 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6322 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5200 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29983 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 180696 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 572523 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106211851 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28585179 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030672 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9774 # number of nop insts executed -system.cpu.iew.exec_refs 49953963 # number of memory reference insts executed -system.cpu.iew.exec_branches 14606559 # Number of branches executed -system.cpu.iew.exec_stores 21356701 # Number of stores executed -system.cpu.iew.exec_rate 1.982126 # Inst execution rate -system.cpu.iew.wb_sent 105847179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105627710 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53336530 # num instructions producing a value -system.cpu.iew.wb_consumers 104015656 # num instructions consuming a value +system.cpu.iew.exec_nop 9806 # number of nop insts executed +system.cpu.iew.exec_refs 49926975 # number of memory reference insts executed +system.cpu.iew.exec_branches 14599283 # Number of branches executed +system.cpu.iew.exec_stores 21341796 # Number of stores executed +system.cpu.iew.exec_rate 1.982275 # Inst execution rate +system.cpu.iew.wb_sent 105782073 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105565164 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53316718 # num instructions producing a value +system.cpu.iew.wb_consumers 103963305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.969927 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512774 # average fanout of values written-back +system.cpu.iew.wb_rate 1.970206 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512842 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11053294 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10921742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 504169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44535629 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.259594 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.766011 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499421 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44519209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.260427 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.765009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15484235 34.77% 34.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11649742 26.16% 60.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3457573 7.76% 68.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2865921 6.44% 75.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1843682 4.14% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1946516 4.37% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 688008 1.54% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565195 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6034757 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15470185 34.75% 34.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11634994 26.13% 60.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3452010 7.75% 68.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2868846 6.44% 75.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1865323 4.19% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1954753 4.39% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 686748 1.54% 85.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 559469 1.26% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6026881 13.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44535629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44519209 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -631,243 +670,243 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6034757 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6026881 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150161295 # The number of ROB reads -system.cpu.rob.rob_writes 225029668 # The number of ROB writes -system.cpu.timesIdled 76463 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7435491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150021199 # The number of ROB reads +system.cpu.rob.rob_writes 224747411 # The number of ROB writes +system.cpu.timesIdled 76674 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7431454 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.756197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.756197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.322408 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.322408 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511842322 # number of integer regfile reads -system.cpu.int_regfile_writes 103400028 # number of integer regfile writes -system.cpu.fp_regfile_reads 836 # number of floating regfile reads -system.cpu.fp_regfile_writes 732 # number of floating regfile writes -system.cpu.misc_regfile_reads 49193821 # number of misc regfile reads +system.cpu.cpi 0.755642 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755642 # CPI: Total CPI of All Threads +system.cpu.ipc 1.323378 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.323378 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511545132 # number of integer regfile reads +system.cpu.int_regfile_writes 103340839 # number of integer regfile writes +system.cpu.fp_regfile_reads 806 # number of floating regfile reads +system.cpu.fp_regfile_writes 694 # number of floating regfile writes +system.cpu.misc_regfile_reads 49339612 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 770392865 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 86565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 86563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107049 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107049 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 516494 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20623232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20623232 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 31040 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290637496 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 773036658 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87363 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87363 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107048 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454686 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 518138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2013952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18662976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20676928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20676928 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33024 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291143497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47495730 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 48712731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260347495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260354993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28815 # number of replacements -system.cpu.icache.tags.tagsinuse 1808.840382 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11662045 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30854 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377.975141 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29638 # number of replacements +system.cpu.icache.tags.tagsinuse 1806.211071 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11640103 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 31672 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 367.520302 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1808.840382 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2039 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1260 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 677 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23425177 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23425177 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11662047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11662047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11662047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11662047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11662047 # number of overall hits -system.cpu.icache.overall_hits::total 11662047 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34957 # number of overall misses -system.cpu.icache.overall_misses::total 34957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 813284976 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 813284976 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 813284976 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 813284976 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 813284976 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 813284976 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11697004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11697004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11697004 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11697004 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11697004 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11697004 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23265.296679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23265.296679 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23265.296679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23265.296679 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2987 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1806.211071 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2034 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.993164 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23383696 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23383696 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11640118 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11640118 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11640118 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11640118 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11640118 # number of overall hits +system.cpu.icache.overall_hits::total 11640118 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35738 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35738 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35738 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35738 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35738 # number of overall misses +system.cpu.icache.overall_misses::total 35738 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 828271479 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 828271479 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 828271479 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 828271479 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 828271479 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 828271479 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11675856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11675856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11675856 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11675856 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11675856 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11675856 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003061 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003061 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003061 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003061 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003061 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23176.212407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23176.212407 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 856 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 129.869565 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3787 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3787 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3787 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3787 # number of demand (read+write) MSHR hits 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miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 659799769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 659799769 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 659799769 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002665 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002665 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002665 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21167.782130 # average ReadReq mshr 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was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks -system.cpu.l2cache.writebacks::total 83947 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 83937 # number of writebacks +system.cpu.l2cache.writebacks::total 83937 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4674 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26531 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4646 # number 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128788 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 308414000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1593918750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1902332750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3088307 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3088307 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7239546250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7239546250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 308414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8833465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9141879000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 308414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8833465000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9141879000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308213 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.959502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.959502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955235 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955235 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.666850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.666850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65985.023534 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72924.863888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71702.263390 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.970779 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.970779 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70797.561536 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70797.561536 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102254 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102254 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124108 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4646 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124108 # number of overall MSHR misses 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9143383750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 311360750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8832023000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9143383750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses 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miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71880.594340 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70789.876191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70789.876191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71164.010378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.032790 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.859504 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993374 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.839586 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993369 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1767 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2268 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2254 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 92301717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 92301717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 26063246 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26063246 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266759 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266759 # number of WriteReq hits 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of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44330005 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44330005 # number of overall hits -system.cpu.dcache.overall_hits::total 44330005 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124539 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124539 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583142 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583142 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707681 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707681 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707681 # number of overall misses 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-system.cpu.dcache.overall_miss_latency::total 132215195206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26187785 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26187785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315381 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315381 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315381 # number of overall hits +system.cpu.dcache.overall_hits::total 44315381 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125140 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125140 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583322 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583322 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 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+system.cpu.dcache.demand_miss_latency::cpu.data 132242138703 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132242138703 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132242138703 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132242138703 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16032 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16032 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16022 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46037686 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46037686 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46037686 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46037686 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004756 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004756 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079756 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079756 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002682 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002682 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037093 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037093 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037093 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037093 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41885.262568 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41885.262568 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80219.491676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80219.491676 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24104.651163 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24104.651163 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77423.825179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77423.825179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3791 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1217 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 149 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.442953 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 93.615385 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023843 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023843 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023843 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023843 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004781 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004781 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079765 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079765 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037121 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037121 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037121 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037121 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77404.202554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77404.202554 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4865 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1223 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.510949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 87.357143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129111 # number of writebacks -system.cpu.dcache.writebacks::total 129111 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475806 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475806 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55429 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55429 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107336 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107336 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162765 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162765 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162765 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162765 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263965562 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263965562 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8681187684 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8681187684 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945153246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10945153246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945153246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129182 # number of writebacks +system.cpu.dcache.writebacks::total 129182 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69727 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69727 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475983 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475983 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545710 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545710 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545710 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545710 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107339 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107339 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162752 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162752 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162752 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162752 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263243564 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263243564 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8680214182 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8680214182 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10943457746 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10943457746 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10943457746 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10943457746 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40844.423713 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40844.423713 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80878.621190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80878.621190 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index b4899830a..ba6e5f41a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index fd88c13a1..b32e4875d 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:25:48 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:03:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x49b6380 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Exiting @ tick 53932157000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 130b6bb56..d5e255546 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1940189 # Simulator instruction rate (inst/s) -host_op_rate 2753308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1475586020 # Simulator tick rate (ticks/s) -host_mem_usage 245844 # Number of bytes of host memory used -host_seconds 36.55 # Real time elapsed on the host +host_inst_rate 1720542 # Simulator instruction rate (inst/s) +host_op_rate 2441608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1308536096 # Simulator tick rate (ticks/s) +host_mem_usage 265732 # Number of bytes of host memory used +host_seconds 41.22 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9230371187 # Th system.membus.data_through_bus 497813828 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 3311620 # nu system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 452177195 # number of times the integer registers were read +system.cpu.num_int_register_reads 452305352 # number of times the integer registers were read system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 8802837e9..de369d8f4 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index 89bb0e0aa..4bb28ef2b 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:26:35 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:04:30 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5604d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Exiting @ tick 132689045000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 7d6b41b45..6c81ce1de 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu sim_ticks 132689045000 # Number of ticks simulated final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019812 # Simulator instruction rate (inst/s) -host_op_rate 1446120 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1922848599 # Simulator tick rate (ticks/s) -host_mem_usage 254584 # Number of bytes of host memory used -host_seconds 69.01 # Real time elapsed on the host +host_inst_rate 945773 # Simulator instruction rate (inst/s) +host_op_rate 1341131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1783248877 # Simulator tick rate (ticks/s) +host_mem_usage 275500 # Number of bytes of host memory used +host_seconds 74.41 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.7 # La system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 3311620 # nu system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read +system.cpu.num_int_register_reads 533671029 # number of times the integer registers were read system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written |