all: Update stats for memory per master and total fix.

9 files changed, 191 insertions, 64 deletions

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 9b36bf976..566c57286 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -525,9 +524,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index f9f6b3025..cb33c4c0f 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:44:00
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:32:39
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index d1da91b90..826f949e8 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -4,23 +4,36 @@ sim_seconds                                  0.024561                       # Nu
 sim_ticks                                 24560764000                       # Number of ticks simulated
 final_tick                                24560764000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54926                       # Simulator instruction rate (inst/s)
-host_op_rate                                    77943                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               19021903                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240316                       # Number of bytes of host memory used
-host_seconds                                  1291.18                       # Real time elapsed on the host
+host_inst_rate                                 104807                       # Simulator instruction rate (inst/s)
+host_op_rate                                   148726                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36296181                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240672                       # Number of bytes of host memory used
+host_seconds                                   676.68                       # Real time elapsed on the host
 sim_insts                                    70920072                       # Number of instructions simulated
 sim_ops                                     100639320                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                     8687232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 367552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  5661632                       # Number of bytes written to this memory
-system.physmem.num_reads                       135738                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       88463                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      353703655                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                  14965007                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                     230515305                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     584218960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            367552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8319680                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8687232                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       367552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          367552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5661632                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5661632                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5743                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             129995                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                135738                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           88463                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                88463                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             14965007                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            338738648                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               353703655                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        14965007                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           14965007                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         230515305                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              230515305                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         230515305                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            14965007                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           338738648                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              584218960                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total     12432222                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     12432222                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     12432222                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002824                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.002824                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.002824                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.002824                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.002824                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.002824                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11568.616839                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 11568.616839                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 11568.616839                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 11568.616839                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 11568.616839                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 11568.616839                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    268782500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    268782500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    268782500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002705                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002705                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002705                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.002705                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002705                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.002705                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7991.392638                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7991.392638                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7991.392638                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7991.392638                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7991.392638                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7991.392638                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 158907                       # number of replacements
 system.cpu.dcache.tagsinuse               4070.754102                       # Cycle average of tags in use
@@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total     46353396                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     46353396                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     46353396                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004158                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004158                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.077587                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.077587                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001779                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001779                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.035602                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.035602                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.035602                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.035602                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22097.370069                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22097.370069                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34105.131348                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34105.131348                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12142.857143                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12142.857143                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 33303.352734                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33303.352734                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33303.352734                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33303.352734                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       203500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total   4716431500
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4716431500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total   4716431500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002117                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005388                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005388                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003518                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003518                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003518                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003518                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18700.810763                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18700.810763                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34284.263770                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34284.263770                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28921.500273                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28921.500273                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28921.500273                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28921.500273                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                115487                       # number of replacements
 system.cpu.l2cache.tagsinuse             18346.494934                       # Cycle average of tags in use
@@ -586,20 +629,30 @@ system.cpu.l2cache.overall_accesses::cpu.data       163003
 system.cpu.l2cache.overall_accesses::total       196558                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.171927                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.489855                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.370843                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.851351                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.851351                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.959483                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.959483                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.171927                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.797899                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.691038                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.171927                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.797899                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.691038                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34232.535968                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34238.943690                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34237.831659                       # average ReadReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   547.619048                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   547.619048                       # average UpgradeReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34314.620761                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34314.620761                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34232.535968                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.635245                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34295.827842                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34232.535968                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.635245                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34295.827842                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -647,20 +700,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4047027000
 system.cpu.l2cache.overall_mshr_miss_latency::total   4225466000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.171152                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.488696                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.369828                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.851351                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.851351                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.959483                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.959483                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.171152                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.797501                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.690575                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.171152                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.797501                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.690575                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31070.694759                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31086.088004                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.421315                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.746032                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31031.746032                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31144.487118                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31144.487118                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31070.694759                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31132.174314                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31129.573148                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31070.694759                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31132.174314                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31129.573148                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 40b740299..311edc8c7 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -112,9 +112,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
index 6e02c2f67..f1623eafd 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:44:19
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:34:04
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 015123589..b5b6453b4 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.053932                       # Nu
 sim_ticks                                 53932162000                       # Number of ticks simulated
 final_tick                                53932162000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 956394                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1357212                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              727373394                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228240                       # Number of bytes of host memory used
-host_seconds                                    74.15                       # Real time elapsed on the host
+host_inst_rate                                1760373                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2498132                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1338828629                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228700                       # Number of bytes of host memory used
+host_seconds                                    40.28                       # Real time elapsed on the host
 sim_insts                                    70913189                       # Number of instructions simulated
 sim_ops                                     100632437                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                   419153654                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read              312580308                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 78660211                       # Number of bytes written to this memory
-system.physmem.num_reads                    105301330                       # Number of read requests responded to by this memory
-system.physmem.num_writes                    19865820                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     7771868185                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                5795805256                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1458502832                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    9230371017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst         312580308                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         106573346                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            419153654                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    312580308                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       312580308                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data       78660211                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          78660211                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst           78145077                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           27156253                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             105301330                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data          19865820                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             19865820                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           5795805256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1976062929                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              7771868185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      5795805256                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         5795805256                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1458502832                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1458502832                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          5795805256                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3434565761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             9230371017                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 6148c904a..678b8b9b7 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -194,9 +193,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index c236a6c17..d480c9ad1 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:17:37
-gem5 started May  8 2012 16:45:44
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 18:34:55
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index f30f52adf..f1e03b8eb 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,23 +4,36 @@ sim_seconds                                  0.133117                       # Nu
 sim_ticks                                133117442000                       # Number of ticks simulated
 final_tick                               133117442000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 457869                       # Simulator instruction rate (inst/s)
-host_op_rate                                   649270                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              866095863                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237424                       # Number of bytes of host memory used
-host_seconds                                   153.70                       # Real time elapsed on the host
+host_inst_rate                                 828989                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1175527                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1568098699                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237868                       # Number of bytes of host memory used
+host_seconds                                    84.89                       # Real time elapsed on the host
 sim_insts                                    70373636                       # Number of instructions simulated
 sim_ops                                      99791663                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                     8570688                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 294208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  5660736                       # Number of bytes written to this memory
-system.physmem.num_reads                       133917                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       88449                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       64384410                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   2210139                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      42524375                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     106908785                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            294208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8276480                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8570688                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       294208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          294208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5660736                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5660736                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4597                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             129320                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                133917                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           88449                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                88449                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2210139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             62174272                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                64384410                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2210139                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2210139                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          42524375                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               42524375                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          42524375                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2210139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            62174272                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              106908785                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total     78145078                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     78145078                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     78145078                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000242                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000242                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000242                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000242                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000242                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24211.233340                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24211.233340                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24211.233340                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    401062000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    401062000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    401062000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000242                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21211.233340                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 155902                       # number of replacements
 system.cpu.dcache.tagsinuse               4076.934010                       # Cycle average of tags in use
@@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total     46990235                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     46990235                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     46990235                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001952                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.001952                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.003405                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.003405                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.003405                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.003405                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35166.521920                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54271.451529                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47946.924337                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47946.924337                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total   7191418000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7191418000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total   7191418000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001952                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001952                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003405                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003405                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32166.521920                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51271.451529                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44946.924337                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44946.924337                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                113660                       # number of replacements
 system.cpu.l2cache.tagsinuse             18191.621028                       # Cycle average of tags in use
@@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data       159998
 system.cpu.l2cache.overall_accesses::total       178906                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.243125                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.503965                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.435345                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.958844                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.958844                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.243125                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.808260                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.748533                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.243125                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.808260                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.748533                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5172800000
 system.cpu.l2cache.overall_mshr_miss_latency::total   5356680000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.243125                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.503965                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.435345                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.958844                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.958844                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.243125                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.808260                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.748533                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.243125                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.808260                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.748533                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------