stats: changes due to recent changesets.

2 files changed, 166 insertions, 112 deletions

diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index e5a2f02e5..b9814d1e2 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -4,33 +4,37 @@ sim_seconds                                  0.057816                       # Nu
 sim_ticks                                 57815555000                       # Number of ticks simulated
 final_tick                                57815555000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 199176                       # Simulator instruction rate (inst/s)
-host_op_rate                                   254717                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              162383906                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 320240                       # Number of bytes of host memory used
-host_seconds                                   356.04                       # Real time elapsed on the host
+host_inst_rate                                 131971                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168772                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              107593052                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309228                       # Number of bytes of host memory used
+host_seconds                                   537.35                       # Real time elapsed on the host
 sim_insts                                    70915127                       # Number of instructions simulated
 sim_ops                                      90690083                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           8247808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            324480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7923328                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8247808                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       324480                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          324480                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      5372864                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           5372864                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst             128872                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               5070                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             123802                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                128872                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           83951                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                83951                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            142657249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              5612330                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            137044918                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total               142657249                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst         5612330                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total            5612330                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks          92931115                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               92931115                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks          92931115                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           142657249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5612330                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           137044918                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              235588364                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        128872                       # Number of read requests accepted
 system.physmem.writeReqs                        83951                       # Number of write requests accepted
@@ -419,8 +423,8 @@ system.cpu.dcache.tags.total_refs            42664902                       # To
 system.cpu.dcache.tags.sampled_refs            160524                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            265.785191                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         784159000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4068.581764                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.993306                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.581764                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993306                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993306                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
@@ -429,61 +433,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2         3299
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          86014590                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         86014590                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     22989229                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     22989229                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        22989229                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     19643835                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19643835                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       19643835                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst        15919                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst        15919                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      42633064                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      42633064                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         42633064                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     42633064                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     42633064                       # number of overall hits
 system.cpu.dcache.overall_hits::total        42633064                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst        56065                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data        56065                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total         56065                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       206066                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       206066                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       206066                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst       262131                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data       262131                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total         262131                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst       262131                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data       262131                       # number of overall misses
 system.cpu.dcache.overall_misses::total        262131                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   2147242437                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2147242437                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total   2147242437                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  15196521000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  15196521000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total  15196521000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  17343763437                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  17343763437                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::total  17343763437                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  17343763437                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  17343763437                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  17343763437                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     23045294                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     23045294                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     23045294                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst        15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     42895195                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     42895195                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     42895195                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     42895195                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42895195                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     42895195                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002433                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002433                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.002433                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.010381                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010381                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.010381                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.006111                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006111                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.006111                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.006111                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.006111                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.006111                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38299.160564                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73745.892093                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66164.488126                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total 66164.488126                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66164.488126                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 66164.488126                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -495,45 +499,45 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       128441                       # number of writebacks
 system.cpu.dcache.writebacks::total            128441                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst         2577                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2577                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total         2577                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        99030                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        99030                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total        99030                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       101607                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       101607                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total       101607                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       101607                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       101607                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total       101607                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        53488                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        53488                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        53488                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       107036                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107036                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       107036                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       160524                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       160524                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total       160524                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       160524                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       160524                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       160524                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   1987609313                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1987609313                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total   1987609313                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   7609976000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7609976000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total   7609976000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst   9597585313                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9597585313                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::total   9597585313                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst   9597585313                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9597585313                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total   9597585313                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002321                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002321                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002321                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.003742                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003742                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.003742                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37159.910877                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71097.350424                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59789.098907                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59789.098907                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             42682                       # number of replacements
@@ -629,9 +633,11 @@ system.cpu.l2cache.tags.sampled_refs           126852                       # Sa
 system.cpu.l2cache.tags.avg_refs             0.785932                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3229.441462                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1563.058609                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1666.382853                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.815049                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.098555                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047701                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.050854                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.913603                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        31119                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
@@ -642,57 +648,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4          583
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949677                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          2903408                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         2903408                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        71548                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst        39644                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        31904                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          71548                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks       128441                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       128441                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst         4755                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4755                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         4755                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        76303                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        39644                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        36659                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total           76303                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        76303                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst        39644                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        36659                       # number of overall hits
 system.cpu.l2cache.overall_hits::total          76303                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        26665                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst         5081                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        21584                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        26665                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       102281                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102281                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       102281                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst       128946                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         5081                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       123865                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        128946                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst       128946                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst         5081                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       123865                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       128946                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1978063750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    363309000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1614754750                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total   1978063750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7455355000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7455355000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total   7455355000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   9433418750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    363309000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   9070109750                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total   9433418750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   9433418750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    363309000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   9070109750                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total   9433418750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        98213                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        44725                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        53488                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        98213                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks       128441                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       128441                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       107036                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       107036                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       107036                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       205249                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        44725                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       160524                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       205249                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       205249                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        44725                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       160524                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       205249                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.271502                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113605                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.403530                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.271502                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.955576                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955576                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.955576                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.628242                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113605                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771629                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.628242                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.628242                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113605                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771629                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.628242                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74182.027002                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71503.444204                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74812.581079                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72890.908380                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.908380                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73157.901370                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71503.444204                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.767973                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73157.901370                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71503.444204                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.767973                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -704,43 +728,58 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        83951                       # number of writebacks
 system.cpu.l2cache.writebacks::total            83951                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           73                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           63                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           73                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           63                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           73                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           63                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           73                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        26592                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5071                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21521                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total        26592                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       102281                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102281                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       102281                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       128873                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         5071                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       123802                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       128873                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       128873                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         5071                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       123802                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       128873                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1635105500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    298810000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1336295500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1635105500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6164329000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6164329000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6164329000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7799434500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    298810000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7500624500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total   7799434500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7799434500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    298810000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7500624500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total   7799434500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.270758                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113382                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.402352                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.270758                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.955576                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955576                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955576                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.627886                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113382                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771237                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.627886                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.627886                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113382                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771237                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.627886                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61488.624398                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58925.261290                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62092.630454                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60268.564054                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60268.564054                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60520.314573                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58925.261290                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60585.648859                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60520.314573                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58925.261290                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60585.648859                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq          98213                       # Transaction distribution
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 6bff9ac08..969dafec8 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -157,6 +157,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -498,6 +499,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -558,6 +560,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -607,6 +610,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -628,19 +632,27 @@ mem_side=system.membus.slave[1]
 
 [system.cpu.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu.l2cache.tags]
@@ -673,6 +685,7 @@ eventq_index=0
 type=LiveProcess
 cmd=vortex lendian.raw
 cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+drivers=
 egid=100
 env=
 errout=cerr
@@ -681,6 +694,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -754,6 +768,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0