diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long/se/50.vortex/ref/arm | |
parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm')
-rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1433 | ||||
-rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt | 432 |
2 files changed, 935 insertions, 930 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index c4dd2ec41..bbe40238a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024118 # Number of seconds simulated -sim_ticks 24118236000 # Number of ticks simulated -final_tick 24118236000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026781 # Number of seconds simulated +sim_ticks 26780535000 # Number of ticks simulated +final_tick 26780535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96109 # Simulator instruction rate (inst/s) -host_op_rate 136382 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32682486 # Simulator tick rate (ticks/s) -host_mem_usage 260548 # Number of bytes of host memory used -host_seconds 737.96 # Real time elapsed on the host -sim_insts 70924474 # Number of instructions simulated -sim_ops 100643721 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 326720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory -system.physmem.bytes_read::total 8354752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 326720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 326720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417408 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417408 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130543 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84647 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84647 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13546596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 332861491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 346408087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13546596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13546596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 224618749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 224618749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 224618749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13546596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 332861491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 571026836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 130544 # Total number of read requests seen -system.physmem.writeReqs 84647 # Total number of write requests seen -system.physmem.cpureqs 215212 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8354752 # Total number of bytes read from memory -system.physmem.bytesWritten 5417408 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8354752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5417408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 21 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8120 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8186 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8038 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5079 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5269 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5401 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5458 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5400 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5357 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5255 # Track writes on a per bank basis +host_inst_rate 149394 # Simulator instruction rate (inst/s) +host_op_rate 211994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56410244 # Simulator tick rate (ticks/s) +host_mem_usage 261852 # Number of bytes of host memory used +host_seconds 474.75 # Real time elapsed on the host +sim_insts 70924159 # Number of instructions simulated +sim_ops 100643406 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 300160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7944448 # Number of bytes read from this memory +system.physmem.bytes_read::total 8244608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 300160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 300160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372672 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128822 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83948 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83948 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11208141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296650086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307858226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11208141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11208141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200618546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200618546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200618546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11208141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296650086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508476772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128823 # Total number of read requests seen +system.physmem.writeReqs 83948 # Total number of write requests seen +system.physmem.cpureqs 213079 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8244608 # Total number of bytes read from memory +system.physmem.bytesWritten 5372672 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8244608 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372672 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 308 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7950 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5174 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5126 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5148 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24118216500 # Total gap between requests +system.physmem.totGap 26780515500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 130544 # Categorize read packet sizes +system.physmem.readPktSize::6 128823 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 84647 # categorize write packet sizes +system.physmem.writePktSize::6 83948 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 21 # categorize neither packet sizes +system.physmem.neitherpktsize::6 308 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 69205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 57726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2308860118 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4224446118 # Sum of mem lat for all requests -system.physmem.totBusLat 522152000 # Total cycles spent in databus access -system.physmem.totBankLat 1393434000 # Total cycles spent in bank access -system.physmem.avgQLat 17687.26 # Average queueing delay per request -system.physmem.avgBankLat 10674.55 # Average bank access latency per request +system.physmem.totQLat 4847041699 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6735959699 # Sum of mem lat for all requests +system.physmem.totBusLat 515280000 # Total cycles spent in databus access +system.physmem.totBankLat 1373638000 # Total cycles spent in bank access +system.physmem.avgQLat 37626.47 # Average queueing delay per request +system.physmem.avgBankLat 10663.24 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32361.81 # Average memory access latency -system.physmem.avgRdBW 346.41 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 224.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 346.41 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 224.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52289.70 # Average memory access latency +system.physmem.avgRdBW 307.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 200.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 307.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 200.62 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.57 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.22 # Average write queue length over time -system.physmem.readRowHits 119025 # Number of row buffer hits during reads -system.physmem.writeRowHits 63519 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes -system.physmem.avgGap 112078.18 # Average gap between requests +system.physmem.busUtil 3.18 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.25 # Average read queue length over time +system.physmem.avgWrQLen 9.64 # Average write queue length over time +system.physmem.readRowHits 118946 # Number of row buffer hits during reads +system.physmem.writeRowHits 27105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.29 # Row buffer hit rate for writes +system.physmem.avgGap 125865.44 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,581 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48236473 # number of cpu cycles simulated +system.cpu.numCycles 53561071 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16941730 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12971297 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 673506 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11955063 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7993850 # Number of BTB hits +system.cpu.BPredUnit.lookups 16989438 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12991194 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 680202 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11755292 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8009849 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1846956 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114386 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12578866 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 86846522 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16941730 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9840806 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21621241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2621679 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9822158 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 11935876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 192083 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45946369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.646136 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.346825 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1851785 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114363 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12914479 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87008149 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16989438 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9861634 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21655288 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2666634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10515039 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 571 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11971869 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 198806 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47045662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.589318 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332778 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24346810 52.99% 52.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2176798 4.74% 57.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2018114 4.39% 62.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2096656 4.56% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1493050 3.25% 69.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1410144 3.07% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 982338 2.14% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1219252 2.65% 77.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10203207 22.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25412140 54.02% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2169507 4.61% 58.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2024864 4.30% 62.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2094897 4.45% 67.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1497374 3.18% 70.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1417625 3.01% 73.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 986770 2.10% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1225872 2.61% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10216613 21.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45946369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351222 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.800433 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14667970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8208523 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19889635 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1362773 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1817468 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3410064 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108805 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118869438 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 371525 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1817468 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16391147 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2180805 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 744758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19482609 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5329582 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116713190 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4505903 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 207 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117071318 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 537479367 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537472531 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6836 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159624 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17911694 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25668 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25645 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12679365 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29945230 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22644975 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3554453 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4308488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112817859 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41708 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108131794 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 320520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12061302 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28451439 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4553 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45946369 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.353435 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.992555 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47045662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317198 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.624466 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15025286 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8880734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19918391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1367786 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1853465 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3434521 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119105730 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 372945 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1853465 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16780714 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2530019 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 932679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19483180 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5465605 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116933277 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4623545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 215 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117254635 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 538431443 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 538426294 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5149 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18095515 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25625 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25611 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12984960 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29963650 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22702028 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3806099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4346835 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113028204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41641 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108286515 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 316116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12256138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28707838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4549 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47045662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.301732 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.993875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10567306 23.00% 23.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8020118 17.46% 40.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7429171 16.17% 56.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7172224 15.61% 72.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5474021 11.91% 84.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3920572 8.53% 92.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1887629 4.11% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 890680 1.94% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 584648 1.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11469393 24.38% 24.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8159881 17.34% 41.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7486298 15.91% 57.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7193710 15.29% 72.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5478307 11.64% 84.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3936871 8.37% 92.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1856294 3.95% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881703 1.87% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 583205 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45946369 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47045662 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112571 4.42% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1415190 55.57% 59.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1018757 40.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112009 4.47% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1372514 54.80% 59.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1019865 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57176824 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91588 0.08% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29115499 26.93% 79.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21747640 20.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57275495 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91732 0.08% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 181 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29138143 26.91% 79.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21780957 20.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108131794 # Type of FU issued -system.cpu.iq.rate 2.241702 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2546520 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023550 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 265076321 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124946354 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106228285 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1064 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 184 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110677977 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2176777 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108286515 # Type of FU issued +system.cpu.iq.rate 2.021739 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2504390 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023127 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266438684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125354112 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106381358 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110790645 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2168801 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2634753 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7333 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27466 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2085868 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2653236 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30261 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2142984 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 473 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1817468 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 825568 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31883 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112869381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 345659 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29945230 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22644975 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25238 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1097 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3023 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27466 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 452017 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 199338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 651355 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106955311 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28765738 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1176483 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1853465 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1042007 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 44975 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113079657 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 348290 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29963650 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22702028 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 25073 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6129 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5511 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30261 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 453510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 204690 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 658200 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107104018 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28789803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1182497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9814 # number of nop insts executed -system.cpu.iew.exec_refs 50205955 # number of memory reference insts executed -system.cpu.iew.exec_branches 14704580 # Number of branches executed -system.cpu.iew.exec_stores 21440217 # Number of stores executed -system.cpu.iew.exec_rate 2.217312 # Inst execution rate -system.cpu.iew.wb_sent 106472209 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106228469 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53599142 # num instructions producing a value -system.cpu.iew.wb_consumers 104275439 # num instructions consuming a value +system.cpu.iew.exec_nop 9812 # number of nop insts executed +system.cpu.iew.exec_refs 50259028 # number of memory reference insts executed +system.cpu.iew.exec_branches 14733119 # Number of branches executed +system.cpu.iew.exec_stores 21469225 # Number of stores executed +system.cpu.iew.exec_rate 1.999662 # Inst execution rate +system.cpu.iew.wb_sent 106622925 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106381514 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53628948 # num instructions producing a value +system.cpu.iew.wb_consumers 104196549 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.202244 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514015 # average fanout of values written-back +system.cpu.iew.wb_rate 1.986172 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514690 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12220612 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37155 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567157 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44128902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.280802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756042 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12431579 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 573556 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45192198 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.227131 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.747743 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14889585 33.74% 33.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11723135 26.57% 60.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3525477 7.99% 68.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2911105 6.60% 74.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1898953 4.30% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1983472 4.49% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685141 1.55% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578421 1.31% 86.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5933613 13.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15976760 35.35% 35.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724717 25.94% 61.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3516948 7.78% 69.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2892652 6.40% 75.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1888504 4.18% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1974510 4.37% 84.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692586 1.53% 85.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 573861 1.27% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5951660 13.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44128902 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70930026 # Number of instructions committed -system.cpu.commit.committedOps 100649273 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45192198 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929711 # Number of instructions committed +system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869584 # Number of memory references committed -system.cpu.commit.loads 27310477 # Number of loads committed +system.cpu.commit.refs 47869458 # Number of memory references committed +system.cpu.commit.loads 27310414 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744874 # Number of branches committed +system.cpu.commit.branches 13744811 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486255 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5933613 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5951660 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 151039875 # The number of ROB reads -system.cpu.rob.rob_writes 227567987 # The number of ROB writes -system.cpu.timesIdled 41986 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2290104 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924474 # Number of Instructions Simulated -system.cpu.committedOps 100643721 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924474 # Number of Instructions Simulated -system.cpu.cpi 0.680110 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.680110 # CPI: Total CPI of All Threads -system.cpu.ipc 1.470350 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.470350 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 514798749 # number of integer regfile reads -system.cpu.int_regfile_writes 104102920 # number of integer regfile writes -system.cpu.fp_regfile_reads 856 # number of floating regfile reads -system.cpu.fp_regfile_writes 720 # number of floating regfile writes -system.cpu.misc_regfile_reads 145263086 # number of misc regfile reads -system.cpu.misc_regfile_writes 38578 # number of misc regfile writes -system.cpu.icache.replacements 29552 # number of replacements -system.cpu.icache.tagsinuse 1826.273597 # Cycle average of tags in use -system.cpu.icache.total_refs 11903209 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31595 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 376.743440 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152295776 # The number of ROB reads +system.cpu.rob.rob_writes 228025366 # The number of ROB writes +system.cpu.timesIdled 74466 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6515409 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924159 # Number of Instructions Simulated +system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated +system.cpu.cpi 0.755188 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755188 # CPI: Total CPI of All Threads +system.cpu.ipc 1.324174 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.324174 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 515451838 # number of integer regfile reads +system.cpu.int_regfile_writes 104231541 # number of integer regfile writes +system.cpu.fp_regfile_reads 698 # number of floating regfile reads +system.cpu.fp_regfile_writes 610 # number of floating regfile writes +system.cpu.misc_regfile_reads 145512549 # number of misc regfile reads +system.cpu.misc_regfile_writes 38452 # number of misc regfile writes +system.cpu.icache.replacements 31300 # number of replacements +system.cpu.icache.tagsinuse 1822.220766 # Cycle average of tags in use +system.cpu.icache.total_refs 11934433 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 33335 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 358.015089 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1826.273597 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.891735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.891735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11903210 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11903210 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11903210 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11903210 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11903210 # number of overall hits -system.cpu.icache.overall_hits::total 11903210 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 32666 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 32666 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 32666 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 32666 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 32666 # number of overall misses -system.cpu.icache.overall_misses::total 32666 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 361659000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 361659000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 361659000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 361659000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 361659000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 361659000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11935876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11935876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11935876 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11935876 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11935876 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11935876 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11071.419825 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11071.419825 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11071.419825 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11071.419825 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1822.220766 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.889756 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.889756 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11934443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11934443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11934443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11934443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11934443 # number of overall hits +system.cpu.icache.overall_hits::total 11934443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 37425 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 37425 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 37425 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 37425 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 37425 # number of overall misses +system.cpu.icache.overall_misses::total 37425 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19194.255150 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.157895 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1048 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1048 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1048 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1048 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1048 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31618 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31618 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31618 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31618 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31618 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 265572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 265572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 265572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 265572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 265572000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 265572000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8399.392751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8399.392751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17513.610264 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158443 # number of replacements -system.cpu.dcache.tagsinuse 4074.275674 # Cycle average of tags in use -system.cpu.dcache.total_refs 44571484 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162539 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.220243 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 222430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4074.275674 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994696 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994696 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26246493 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26246493 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18285066 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18285066 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20587 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20587 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19288 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19288 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44531559 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44531559 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44523515 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44523515 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44523515 # number of overall hits +system.cpu.dcache.overall_hits::total 44523515 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125393 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125393 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584834 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584834 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1710227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1710227 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1710227 # number of overall misses +system.cpu.dcache.overall_misses::total 1710227 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4597179000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4597179000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120104513482 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120104513482 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124701692482 # 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miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036144 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036144 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036144 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24747.305993 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24747.305993 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38468.092802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38468.092802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12121.621622 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12121.621622 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37604.953760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37604.953760 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 149 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.555556 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20499 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20499 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # 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miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036991 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036991 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036991 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036991 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36662.166150 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36662.166150 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75783.655248 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75783.655248 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21568.181818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21568.181818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72915.286966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72915.286966 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2506 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 608 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.418803 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128088 # number of writebacks -system.cpu.dcache.writebacks::total 128088 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49495 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49495 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457827 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1457827 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1507322 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1507322 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1507322 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1507322 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55553 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5361060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5361060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5361060500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5361060500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129149 # number of writebacks +system.cpu.dcache.writebacks::total 129149 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69778 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69778 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477521 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477521 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1547299 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1547299 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1547299 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1547299 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55615 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55615 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107313 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107313 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162928 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162928 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162928 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162928 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2039094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2039094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257233993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257233993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10296327993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10296327993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10296327993 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10296327993 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1383.020531 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1869.742346 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.820525 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.042206 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.057060 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.919792 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28461 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 62098 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129149 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129149 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210199490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8190613321 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8400812811 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.393642 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299384 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955439 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955439 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.658029 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.658029 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44809.100405 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62434.674345 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59322.835152 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10007.493506 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 88647a82b..9156fbcd7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132746 # Number of seconds simulated -sim_ticks 132746076000 # Number of ticks simulated -final_tick 132746076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132689 # Number of seconds simulated +sim_ticks 132689045000 # Number of ticks simulated +final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594787 # Simulator instruction rate (inst/s) -host_op_rate 843423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1121948184 # Simulator tick rate (ticks/s) -host_mem_usage 240564 # Number of bytes of host memory used -host_seconds 118.32 # Real time elapsed on the host +host_inst_rate 796611 # Simulator instruction rate (inst/s) +host_op_rate 1129615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1502004709 # Simulator tick rate (ticks/s) +host_mem_usage 239164 # Number of bytes of host memory used +host_seconds 88.34 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8003456 # Number of bytes read from this memory -system.physmem.bytes_read::total 8277184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 273728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 273728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5403392 # Number of bytes written to this memory -system.physmem.bytes_written::total 5403392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2062042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60291470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 62353512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2062042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2062042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40704721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40704721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40704721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2062042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60291470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 103058233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory +system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory +system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 265492152 # number of cpu cycles simulated +system.cpu.numCycles 265378090 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 265492152 # Number of busy cycles +system.cpu.num_busy_cycles 265378090 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.430287 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.430287 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847866 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847866 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 425522000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 425522000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 425522000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 425522000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 425522000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 425522000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22504.865665 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22504.865665 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22504.865665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22504.865665 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387706000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 387706000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387706000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 387706000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387706000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 387706000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20504.865665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20504.865665 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.962537 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.962537 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995352 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995352 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1642566000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1642566000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689754000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689754000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7332320000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7332320000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7332320000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7332320000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31011.705622 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31011.705622 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53159.372898 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53159.372898 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45827.572845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45827.572845 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 127057 # number of writebacks -system.cpu.dcache.writebacks::total 127057 # number of writebacks +system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks +system.cpu.dcache.writebacks::total 128239 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536634000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536634000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475690000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475690000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012324000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7012324000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012324000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7012324000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29011.705622 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29011.705622 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.372898 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.372898 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 96735 # number of replacements -system.cpu.l2cache.tagsinuse 28875.776749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 94693 # number of replacements +system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26451.163706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 950.000997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1474.612046 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.807225 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.028992 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.881219 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 127057 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 127057 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4691 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4691 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 34944 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 49575 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 34944 # number of overall hits -system.cpu.l2cache.overall_hits::total 49575 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4277 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 22713 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26990 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102341 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102341 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4277 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125054 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses -system.cpu.l2cache.overall_misses::total 129331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222488000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181138000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1403626000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321748000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5321748000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 222488000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6502886000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6725374000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 222488000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6502886000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6725374000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits +system.cpu.l2cache.overall_hits::total 51094 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses +system.cpu.l2cache.overall_misses::total 127812 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207838000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1126741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1334579000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5318574000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5318574000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207838000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6445315000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6653153000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207838000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6445315000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6653153000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 127057 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 127057 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.226201 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.428822 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.375518 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956172 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.956172 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.226201 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.781597 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.722899 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52019.639935 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.729714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.409411 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.156340 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.156340 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.252600 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.252600 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 84428 # number of writebacks -system.cpu.l2cache.writebacks::total 84428 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4277 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22713 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26990 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102341 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125054 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 129331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171164000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908582000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079746000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093656000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093656000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002238000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5173402000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002238000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5173402000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956172 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956172 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40019.639935 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.729714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.409411 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.156340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.156340 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks +system.cpu.l2cache.writebacks::total 83909 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |