diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/50.vortex/ref/arm | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm')
6 files changed, 679 insertions, 679 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 33fd8bc7c..0878a1dc0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 462a53b1f..c4aefb2c9 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:13:16 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:29:16 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 23981004500 because target called exit() +Exiting @ tick 24460150500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 8d4101747..f26f3a389 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023981 # Number of seconds simulated -sim_ticks 23981004500 # Number of ticks simulated -final_tick 23981004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024460 # Number of seconds simulated +sim_ticks 24460150500 # Number of ticks simulated +final_tick 24460150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169152 # Simulator instruction rate (inst/s) -host_op_rate 240031 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57193739 # Simulator tick rate (ticks/s) -host_mem_usage 242580 # Number of bytes of host memory used -host_seconds 419.29 # Real time elapsed on the host -sim_insts 70924419 # Number of instructions simulated -sim_ops 100643666 # Number of ops (including micro ops) simulated +host_inst_rate 167024 # Simulator instruction rate (inst/s) +host_op_rate 237012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57603012 # Simulator tick rate (ticks/s) +host_mem_usage 242500 # Number of bytes of host memory used +host_seconds 424.63 # Real time elapsed on the host +sim_insts 70923824 # Number of instructions simulated +sim_ops 100643071 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8029184 # Number of bytes read from this memory -system.physmem.bytes_read::total 8356160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8028736 # Number of bytes read from this memory +system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417856 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417856 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 5417152 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417152 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125456 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84654 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84654 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13634792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 334814332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 348449124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13634792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13634792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 225922813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 225922813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 225922813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13634792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 334814332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 574371937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 125449 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84643 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84643 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13367702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 328237392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 341605094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13367702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13367702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 221468466 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 221468466 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 221468466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13367702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 328237392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 563073559 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 47962010 # number of cpu cycles simulated +system.cpu.numCycles 48920302 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16947214 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12982117 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 655322 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11804628 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7961599 # Number of BTB hits +system.cpu.BPredUnit.lookups 16960531 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12985874 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 661473 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11570513 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7976664 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1880669 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114490 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12764738 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87540471 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16947214 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9842268 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21772804 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2768546 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10027678 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12061426 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 218802 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46590944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.639937 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.350838 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1883015 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 115088 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12843999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87580035 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16960531 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9859679 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21787094 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2782746 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10982319 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 606 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12079139 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 221673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47647021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582724 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336366 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24839551 53.31% 53.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2175787 4.67% 57.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1999394 4.29% 62.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2026993 4.35% 66.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1551688 3.33% 69.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1408138 3.02% 72.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 990048 2.12% 75.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1240896 2.66% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10358449 22.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25881368 54.32% 54.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2178299 4.57% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2007274 4.21% 63.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2021463 4.24% 67.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1548956 3.25% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1412983 2.97% 73.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 995678 2.09% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1240946 2.60% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10360054 21.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46590944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.353347 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.825204 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14883106 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8408681 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19993372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1386692 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1919093 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3458129 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108409 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120163882 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 373498 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1919093 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16645469 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2316120 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 802815 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19569476 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5337971 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117636894 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9686 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4512387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 221 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117778889 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541771281 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541766916 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4365 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159536 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18619353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37368 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37363 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12895568 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30067923 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22776958 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3590168 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4248242 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113315749 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51911 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108455143 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 350648 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12554662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29999283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14767 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46590944 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.327816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.997244 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47647021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346697 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.790259 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15031484 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9298191 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19969978 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1421734 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1925634 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3462876 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109476 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120212842 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 378015 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1925634 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16795731 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2963104 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 805180 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19544890 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5612482 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117675747 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12709 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4780104 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 263 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117787272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541948309 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541940540 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99158584 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18628688 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37002 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 36987 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13169886 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30082364 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22781735 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3607820 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4315548 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113341575 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51734 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108469975 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 351751 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12575588 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30093615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14709 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47647021 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.276532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995144 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11127507 23.88% 23.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8067707 17.32% 41.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7375197 15.83% 57.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7162683 15.37% 72.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5557871 11.93% 84.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3930157 8.44% 92.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1905355 4.09% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881142 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 583325 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11903537 24.98% 24.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8354851 17.53% 42.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7454693 15.65% 58.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7158692 15.02% 73.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5519097 11.58% 84.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3907609 8.20% 92.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1895733 3.98% 96.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881641 1.85% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571168 1.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46590944 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47647021 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112830 4.40% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1425910 55.61% 60.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1025351 39.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112989 4.45% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1419251 55.85% 60.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1008989 39.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57362458 52.89% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91498 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57363382 52.88% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91507 0.08% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 129 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 228 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued @@ -239,160 +239,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29209051 26.93% 79.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21792000 20.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29217041 26.94% 79.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21797810 20.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108455143 # Type of FU issued -system.cpu.iq.rate 2.261272 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2564091 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023642 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 266415556 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125949072 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106420629 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111019028 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 206 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2223683 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108469975 # Type of FU issued +system.cpu.iq.rate 2.217279 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2541231 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023428 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 267479180 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125995514 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106424512 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 773 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1272 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 111010818 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 388 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2214998 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2757457 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7931 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28755 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2217862 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2772017 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7458 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2222758 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1919093 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 944512 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 30820 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113447794 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342667 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30067923 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22776958 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35363 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1047 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28755 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 424789 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263529 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 688318 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107242187 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28840669 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1212956 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1925634 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 929341 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37355 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113473181 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 343640 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30082364 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22781735 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35157 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2560 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3541 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 428613 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 264355 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 692968 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107247329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28841677 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1222646 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80134 # number of nop insts executed -system.cpu.iew.exec_refs 50312690 # number of memory reference insts executed -system.cpu.iew.exec_branches 14662886 # Number of branches executed -system.cpu.iew.exec_stores 21472021 # Number of stores executed -system.cpu.iew.exec_rate 2.235982 # Inst execution rate -system.cpu.iew.wb_sent 106754958 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106420762 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53610539 # num instructions producing a value -system.cpu.iew.wb_consumers 104702454 # num instructions consuming a value +system.cpu.iew.exec_nop 79872 # number of nop insts executed +system.cpu.iew.exec_refs 50315882 # number of memory reference insts executed +system.cpu.iew.exec_branches 14663606 # Number of branches executed +system.cpu.iew.exec_stores 21474205 # Number of stores executed +system.cpu.iew.exec_rate 2.192287 # Inst execution rate +system.cpu.iew.wb_sent 106761196 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106424699 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53424049 # num instructions producing a value +system.cpu.iew.wb_consumers 103788661 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.218855 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512028 # average fanout of values written-back +system.cpu.iew.wb_rate 2.175471 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514739 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 70929971 # The number of committed instructions -system.cpu.commit.commitCommittedOps 100649218 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 12799085 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37144 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 611847 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44671852 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.253079 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.750865 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 70929376 # The number of committed instructions +system.cpu.commit.commitCommittedOps 100648623 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12825262 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37025 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 616891 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45721388 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.201347 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.733819 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15424353 34.53% 34.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11724908 26.25% 60.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3540913 7.93% 68.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2916552 6.53% 75.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1906207 4.27% 79.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1948042 4.36% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 684228 1.53% 85.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 590770 1.32% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5935879 13.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16264410 35.57% 35.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11914734 26.06% 61.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3626051 7.93% 69.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2926022 6.40% 75.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880797 4.11% 80.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1911030 4.18% 84.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 689200 1.51% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 582969 1.28% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5926175 12.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44671852 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929971 # Number of instructions committed -system.cpu.commit.committedOps 100649218 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45721388 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929376 # Number of instructions committed +system.cpu.commit.committedOps 100648623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869562 # Number of memory references committed -system.cpu.commit.loads 27310466 # Number of loads committed +system.cpu.commit.refs 47869324 # Number of memory references committed +system.cpu.commit.loads 27310347 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671985 # Number of branches committed +system.cpu.commit.branches 13671866 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486211 # Number of committed integer instructions. +system.cpu.commit.int_insts 91485735 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5935879 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5926175 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 152158977 # The number of ROB reads -system.cpu.rob.rob_writes 228826081 # The number of ROB writes -system.cpu.timesIdled 61655 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1371066 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924419 # Number of Instructions Simulated -system.cpu.committedOps 100643666 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924419 # Number of Instructions Simulated -system.cpu.cpi 0.676241 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.676241 # CPI: Total CPI of All Threads -system.cpu.ipc 1.478762 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.478762 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516206868 # number of integer regfile reads -system.cpu.int_regfile_writes 104370444 # number of integer regfile writes -system.cpu.fp_regfile_reads 520 # number of floating regfile reads -system.cpu.fp_regfile_writes 444 # number of floating regfile writes -system.cpu.misc_regfile_reads 146052754 # number of misc regfile reads -system.cpu.misc_regfile_writes 38556 # number of misc regfile writes -system.cpu.icache.replacements 29824 # number of replacements -system.cpu.icache.tagsinuse 1820.810833 # Cycle average of tags in use -system.cpu.icache.total_refs 12028408 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31867 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 377.456554 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 153243799 # The number of ROB reads +system.cpu.rob.rob_writes 228884039 # The number of ROB writes +system.cpu.timesIdled 52429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1273281 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70923824 # Number of Instructions Simulated +system.cpu.committedOps 100643071 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70923824 # Number of Instructions Simulated +system.cpu.cpi 0.689758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.689758 # CPI: Total CPI of All Threads +system.cpu.ipc 1.449783 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.449783 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516242048 # number of integer regfile reads +system.cpu.int_regfile_writes 104369908 # number of integer regfile writes +system.cpu.fp_regfile_reads 886 # number of floating regfile reads +system.cpu.fp_regfile_writes 750 # number of floating regfile writes +system.cpu.misc_regfile_reads 146091713 # number of misc regfile reads +system.cpu.misc_regfile_writes 38318 # number of misc regfile writes +system.cpu.icache.replacements 30244 # number of replacements +system.cpu.icache.tagsinuse 1815.033473 # Cycle average of tags in use +system.cpu.icache.total_refs 12045499 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32282 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 373.133604 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1820.810833 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.889068 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.889068 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12028408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12028408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12028408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12028408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12028408 # number of overall hits -system.cpu.icache.overall_hits::total 12028408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33018 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33018 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33018 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33018 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33018 # number of overall misses -system.cpu.icache.overall_misses::total 33018 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 367424500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 367424500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 367424500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 367424500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 367424500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 367424500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12061426 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12061426 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12061426 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12061426 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12061426 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12061426 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11128.005936 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11128.005936 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11128.005936 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11128.005936 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1815.033473 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.886247 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.886247 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12045501 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12045501 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12045501 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12045501 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12045501 # number of overall hits +system.cpu.icache.overall_hits::total 12045501 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33638 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33638 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33638 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33638 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33638 # number of overall misses +system.cpu.icache.overall_misses::total 33638 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 406685000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 406685000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 406685000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 406685000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 406685000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 406685000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12079139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12079139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12079139 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12079139 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12079139 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12079139 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002785 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002785 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002785 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002785 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002785 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002785 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12090.046971 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12090.046971 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,254 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1111 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1111 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1111 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1111 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1111 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31907 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31907 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31907 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31907 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244055000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 244055000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244055000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 244055000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244055000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 244055000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002645 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002645 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002645 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7648.948507 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7648.948507 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1313 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1313 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1313 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1313 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1313 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1313 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32325 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32325 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32325 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32325 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32325 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32325 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274223500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 274223500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274223500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 274223500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274223500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 274223500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8483.325599 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8483.325599 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158597 # number of replacements -system.cpu.dcache.tagsinuse 4071.944277 # Cycle average of tags in use -system.cpu.dcache.total_refs 44611539 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162693 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.206874 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 262057000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.944277 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994127 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994127 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26269994 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26269994 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18301608 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18301608 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20534 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20534 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19277 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19277 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44571602 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44571602 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44571602 # number of overall hits -system.cpu.dcache.overall_hits::total 44571602 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 105369 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 105369 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1548293 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1548293 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1653662 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1653662 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1653662 # number of overall misses -system.cpu.dcache.overall_misses::total 1653662 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2114831500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2114831500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52578719498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52578719498 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 447000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54693550998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54693550998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54693550998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54693550998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26375363 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26375363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 158501 # number of replacements +system.cpu.dcache.tagsinuse 4071.855185 # Cycle average of tags in use +system.cpu.dcache.total_refs 44605412 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162597 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.331089 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4071.855185 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26278291 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26278291 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18287500 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18287500 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20317 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20317 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19158 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19158 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44565791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44565791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44565791 # number of overall hits +system.cpu.dcache.overall_hits::total 44565791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 106674 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 106674 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1562401 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1562401 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1669075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1669075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1669075 # number of overall misses +system.cpu.dcache.overall_misses::total 1669075 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2574319000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2574319000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63349260500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63349260500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 629500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 629500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 65923579500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 65923579500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 65923579500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 65923579500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26384965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26384965 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20573 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20573 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19277 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19277 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46225264 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46225264 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46225264 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46225264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003995 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003995 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078000 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078000 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001896 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001896 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035774 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035774 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.035774 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.035774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20070.718143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20070.718143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33959.153402 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33959.153402 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11461.538462 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11461.538462 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33074.201982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33074.201982 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20360 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20360 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19158 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19158 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46234866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46234866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46234866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46234866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004043 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078711 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078711 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002112 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002112 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036100 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036100 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036100 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036100 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39497.074427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39497.074427 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 202500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128124 # number of writebacks -system.cpu.dcache.writebacks::total 128124 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49671 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49671 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1441258 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1441258 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1490929 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1490929 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1490929 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1490929 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55698 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128059 # number of writebacks +system.cpu.dcache.writebacks::total 128059 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51068 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51068 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1455366 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1455366 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1506434 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1506434 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1506434 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1506434 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55606 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55606 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162733 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162733 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162733 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162733 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 907626500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 907626500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3661924998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3661924998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4569551498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4569551498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4569551498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4569551498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 162641 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162641 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162641 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162641 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 982100000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 982100000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3836030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3836030000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4818130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4818130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4818130000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4818130000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002107 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16295.495350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16295.495350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34212.407138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34212.407138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 97993 # number of replacements -system.cpu.l2cache.tagsinuse 28658.689941 # Cycle average of tags in use -system.cpu.l2cache.total_refs 86749 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128784 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.673601 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 97988 # number of replacements +system.cpu.l2cache.tagsinuse 28616.670846 # Cycle average of tags in use +system.cpu.l2cache.total_refs 87010 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128775 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.675675 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25863.719355 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1158.363470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1636.607116 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.789298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035350 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.874594 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26734 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32452 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59186 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128124 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128124 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4717 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4717 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26734 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 37169 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 63903 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26734 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 37169 # number of overall hits -system.cpu.l2cache.overall_hits::total 63903 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5128 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 23210 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 28338 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 25808.135877 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1157.314936 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1651.220033 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.787602 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035318 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.050391 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.873311 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 27137 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 32372 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 59509 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 794795000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 970500500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3514306000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3514306000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 175705500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4309101000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4484806500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 175705500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4309101000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4484806500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 31862 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.669971 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32088.667058 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32536.865762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32455.800616 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31679.731407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31679.731407 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index c08fcfcdd..4c2746778 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index b1460f18e..564b30c1c 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:20:08 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:37:12 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 132924820000 because target called exit() +Exiting @ tick 133513136000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index b1eb24a6a..250f6daa7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132925 # Number of seconds simulated -sim_ticks 132924820000 # Number of ticks simulated -final_tick 132924820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133513 # Number of seconds simulated +sim_ticks 133513136000 # Number of ticks simulated +final_tick 133513136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112405 # Simulator instruction rate (inst/s) -host_op_rate 1577419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2101158995 # Simulator tick rate (ticks/s) -host_mem_usage 240528 # Number of bytes of host memory used -host_seconds 63.26 # Real time elapsed on the host +host_inst_rate 1170283 # Simulator instruction rate (inst/s) +host_op_rate 1659492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2220265254 # Simulator tick rate (ticks/s) +host_mem_usage 240448 # Number of bytes of host memory used +host_seconds 60.13 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 125054 # Nu system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2059269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60210396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 62269665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2059269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2059269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40649985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40649985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40649985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2059269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60210396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102919650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2050195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59945083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61995278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2050195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2050195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40470864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40470864 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40470864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2050195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59945083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102466142 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 265849640 # number of cpu cycles simulated +system.cpu.numCycles 267026272 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 265849640 # Number of busy cycles +system.cpu.num_busy_cycles 267026272 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.286948 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1735.470121 # Cycle average of tags in use system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.286948 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847796 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847796 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1735.470121 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847398 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847398 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 444346000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 444346000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 444346000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 444346000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 444346000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 444346000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 445311000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 445311000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 445311000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 445311000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 445311000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 445311000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23500.423101 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23500.423101 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23500.423101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23500.423101 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23551.459700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23551.459700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23551.459700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23551.459700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23551.459700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387622000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 387622000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387622000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 387622000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387622000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 387622000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 388587000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 388587000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 388587000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 388587000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 388587000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 388587000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20500.423101 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20500.423101 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20551.459700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20551.459700 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20551.459700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20551.459700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.906689 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.664624 # Cycle average of tags in use system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1079631000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.906689 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995339 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1111220000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.664624 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1695470000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1695470000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5796770000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5796770000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7492240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7492240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7492240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7492240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1699159000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1699159000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5797120000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5797120000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7496279000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7496279000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7496279000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7496279000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32010.535060 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32010.535060 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54159.223410 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54159.223410 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46827.085339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46827.085339 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32080.183514 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32080.183514 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54162.493460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54162.493460 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46852.329404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46852.329404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46852.329404 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536572000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536572000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012246000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7012246000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012246000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7012246000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1540261000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1540261000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5476024000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5476024000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7016285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7016285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7016285000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7016285000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29010.535060 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29010.535060 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.223410 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.223410 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.183514 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29080.183514 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51162.493460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51162.493460 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43852.329404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43852.329404 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 96735 # number of replacements -system.cpu.l2cache.tagsinuse 28872.647154 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 28857.116422 # Cycle average of tags in use system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26446.371833 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 949.934371 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1476.340950 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.807079 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.028990 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.881123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 26427.849240 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 949.438432 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1479.828749 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.806514 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.028975 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.045161 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.880649 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits |