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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
| commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
| tree | 64b85031cb791a21af6059778384d358d992b817 /tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout | |
| parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
| download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz | |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout')
| -rwxr-xr-x | tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 0a5ffdd78..806d3e418 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simout +Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:18:28 -gem5 executing on zizzer +gem5 compiled Jan 23 2013 15:49:24 +gem5 started Jan 23 2013 16:08:27 +gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... |