diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long/se/50.vortex/ref/sparc | |
parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long/se/50.vortex/ref/sparc')
-rw-r--r-- | tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt | 434 |
1 files changed, 217 insertions, 217 deletions
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 1d85fdbdf..ea44c1e9f 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202343 # Number of seconds simulated -sim_ticks 202342809000 # Number of ticks simulated -final_tick 202342809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202242 # Number of seconds simulated +sim_ticks 202242260000 # Number of ticks simulated +final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1232815 # Simulator instruction rate (inst/s) -host_op_rate 1248778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1856050290 # Simulator tick rate (ticks/s) -host_mem_usage 230736 # Number of bytes of host memory used -host_seconds 109.02 # Real time elapsed on the host +host_inst_rate 1258181 # Simulator instruction rate (inst/s) +host_op_rate 1274472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1893298806 # Simulator tick rate (ticks/s) +host_mem_usage 233128 # Number of bytes of host memory used +host_seconds 106.82 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory -system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 665664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 665664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5301376 # Number of bytes written to this memory -system.physmem.bytes_written::total 5301376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3289783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39072859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 42362642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3289783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3289783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26199972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26199972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26199972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3289783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39072859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68562614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory +system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory +system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404685618 # number of cpu cycles simulated +system.cpu.numCycles 404484520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 404685618 # Number of busy cycles +system.cpu.num_busy_cycles 404484520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.814192 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 144074079000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.814192 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978913 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2868177000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2868177000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2868177000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2868177000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2868177000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2868177000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15335.876679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15335.876679 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15335.876679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15335.876679 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494129000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2494129000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494129000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2494129000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494129000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2494129000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.876679 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.876679 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.652500 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.652500 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997962 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997962 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1523847000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1523847000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5622992000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5622992000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7146839000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7146839000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7146839000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7146839000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33491.878942 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33491.878942 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53468.791602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53468.791602 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47435.926538 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47435.926538 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 122378 # number of writebacks -system.cpu.dcache.writebacks::total 122378 # number of writebacks +system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks +system.cpu.dcache.writebacks::total 123970 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432849000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432849000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845513000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6845513000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845513000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6845513000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31491.878942 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31491.878942 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 101560 # number of replacements -system.cpu.l2cache.tagsinuse 29290.996090 # Cycle average of tags in use -system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 98540 # number of replacements +system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129534 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.751918 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 24775.786415 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3266.546663 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1248.663012 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.756097 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.099687 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.038106 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893890 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 122378 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 122378 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3844 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3844 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 176623 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 27145 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 203768 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 176623 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 27145 # number of overall hits -system.cpu.l2cache.overall_hits::total 203768 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 10401 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 22198 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32599 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101335 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101335 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10401 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123533 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 133934 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10401 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123533 # number of overall misses -system.cpu.l2cache.overall_misses::total 133934 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540875000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154340000 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 206169 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 177782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 28387 # number of overall hits +system.cpu.l2cache.overall_hits::total 206169 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 9242 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21035 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 30277 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101256 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101256 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9242 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 122291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 131533 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses +system.cpu.l2cache.overall_misses::total 131533 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 480789000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1574763000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5265313000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5265313000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 480789000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6359287000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6840076000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 480789000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6359287000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6840076000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 122378 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 122378 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123970 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses @@ -316,28 +316,28 @@ system.cpu.l2cache.demand_accesses::total 337702 # n system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.055613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.487879 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.140197 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963453 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.963453 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.055613 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.819848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.396604 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.055613 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.819848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.396604 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.211326 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.982161 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.055278 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.500246 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.500246 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.009876 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.009876 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52002.736956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52002.736956 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,52 +346,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.396604 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.396604 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.211326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.982161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.055278 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks +system.cpu.l2cache.writebacks::total 82868 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |