stats: Update stats for syscall emulation Linux kernel changes.

6 files changed, 114 insertions, 114 deletions

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 49574e0d6..dd4ef298a 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index ea448ddba..0a5ffdd78 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:58:33
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:18:28
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 68148678500 because target called exit()
+Exiting @ tick 68148672000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 158c6976f..932598cf9 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.068149                       # Number of seconds simulated
-sim_ticks                                 68148678500                       # Number of ticks simulated
-final_tick                                68148678500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                 68148672000                       # Number of ticks simulated
+final_tick                                68148672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2876458                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2913702                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1458542737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222372                       # Number of bytes of host memory used
-host_seconds                                    46.72                       # Real time elapsed on the host
-sim_insts                                   134398975                       # Number of instructions simulated
-sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst         538214332                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         147559361                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            685773693                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    538214332                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       538214332                       # Number of instructions bytes read from this memory
+host_inst_rate                                2819750                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2856259                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1429788311                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230172                       # Number of bytes of host memory used
+host_seconds                                    47.66                       # Real time elapsed on the host
+sim_insts                                   134398962                       # Number of instructions simulated
+sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst         538214280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         147559360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            685773640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    538214280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       538214280                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data       89882950                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          89882950                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          134553583                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           37231301                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             171784884                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          134553570                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           37231300                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             171784870                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          20864304                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             20864304                       # Number of write requests responded to by this memory
 system.physmem.num_other::cpu.data              15916                       # Number of other requests responded to by this memory
 system.physmem.num_other::total                 15916                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7897648844                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2165256381                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10062905226                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7897648844                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7897648844                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1318924328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1318924328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7897648844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3484180709                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11381829554                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           7897648835                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2165256573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10062905408                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7897648835                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7897648835                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1318924454                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1318924454                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7897648835                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3484181027                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11381829862                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        136297358                       # number of cpu cycles simulated
+system.cpu.numCycles                        136297345                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   134398975                       # Number of instructions committed
-system.cpu.committedOps                     136139203                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.committedInsts                   134398962                       # Number of instructions committed
+system.cpu.committedOps                     136139190                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             115187746                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
 system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8898970                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8898969                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    115187746                       # number of integer instructions
 system.cpu.num_fp_insts                       2326977                       # number of float instructions
-system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          113147747                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           263032361                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113147734                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      58160249                       # number of memory refs
-system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_mem_refs                      58160248                       # number of memory refs
+system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  136297358                       # Number of busy cycles
+system.cpu.num_busy_cycles                  136297345                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 221d86591..a3a928813 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index 98fb0b2cd..3a91ca093 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 12:32:55
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:19:26
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 204097192000 because target called exit()
+Exiting @ tick 204097178000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index a6ef18324..fbfcfb090 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.204097                       # Number of seconds simulated
-sim_ticks                                204097192000                       # Number of ticks simulated
-final_tick                               204097192000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                204097178000                       # Number of ticks simulated
+final_tick                               204097178000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1236624                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1252636                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1877926206                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229284                       # Number of bytes of host memory used
-host_seconds                                   108.68                       # Real time elapsed on the host
-sim_insts                                   134398975                       # Number of instructions simulated
-sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1441199                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1459859                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2188591939                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238748                       # Number of bytes of host memory used
+host_seconds                                    93.26                       # Real time elapsed on the host
+sim_insts                                   134398962                       # Number of instructions simulated
+sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            665664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7906112                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8571776                       # Number of bytes read from this memory
@@ -24,54 +24,54 @@ system.physmem.num_reads::total                133934                       # Nu
 system.physmem.num_writes::writebacks           82834                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                82834                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst              3261505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             38736995                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                41998500                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             38736998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                41998503                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst         3261505                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total            3261505                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          25974762                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               25974762                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          25974762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks          25974764                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               25974764                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          25974764                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst             3261505                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            38736995                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               67973262                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            38736998                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               67973267                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        408194384                       # number of cpu cycles simulated
+system.cpu.numCycles                        408194356                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   134398975                       # Number of instructions committed
-system.cpu.committedOps                     136139203                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.committedInsts                   134398962                       # Number of instructions committed
+system.cpu.committedOps                     136139190                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             115187746                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
 system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8898970                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8898969                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    115187746                       # number of integer instructions
 system.cpu.num_fp_insts                       2326977                       # number of float instructions
-system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          113147746                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           263032361                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113147733                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      58160249                       # number of memory refs
-system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_mem_refs                      58160248                       # number of memory refs
+system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  408194384                       # Number of busy cycles
+system.cpu.num_busy_cycles                  408194356                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                 184976                       # number of replacements
-system.cpu.icache.tagsinuse               2004.409813                       # Cycle average of tags in use
-system.cpu.icache.total_refs                134366560                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               2004.409949                       # Cycle average of tags in use
+system.cpu.icache.total_refs                134366547                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 718.445547                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           145330300000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    2004.409813                       # Average occupied blocks per requestor
+system.cpu.icache.avg_refs                 718.445478                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           145330286000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst    2004.409949                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.978716                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.978716                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    134366560                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       134366560                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     134366560                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        134366560                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    134366560                       # number of overall hits
-system.cpu.icache.overall_hits::total       134366560                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    134366547                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       134366547                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     134366547                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        134366547                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    134366547                       # number of overall hits
+system.cpu.icache.overall_hits::total       134366547                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst       187024                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        187024                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst       187024                       # number of demand (read+write) misses
@@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst   3060544000
 system.cpu.icache.demand_miss_latency::total   3060544000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst   3060544000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total   3060544000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    134553584                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    134553584                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    134553584                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    134553584                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    134553584                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    134553584                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    134553571                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    134553571                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    134553571                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    134553571                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    134553571                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    134553571                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001390                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.001390                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.001390                       # miss rate for demand accesses
@@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 146582                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.412837                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4087.413116                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 57960842                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              812044000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.412837                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                 384.666919                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              812030000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4087.413116                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997904                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997904                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     37185802                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        37185802                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     37185801                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        37185801                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       20759140                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data        15901                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total           15901                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data      57944942                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         57944942                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     57944942                       # number of overall hits
-system.cpu.dcache.overall_hits::total        57944942                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      57944941                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         57944941                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     57944941                       # number of overall hits
+system.cpu.dcache.overall_hits::total        57944941                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data        45499                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total         45499                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       105164                       # number of WriteReq misses
@@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data   7299977000
 system.cpu.dcache.demand_miss_latency::total   7299977000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data   7299977000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total   7299977000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     37231301                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     37231301                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     37231300                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     37231300                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20864304                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data        15916                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total        15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     58095605                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     58095605                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     58095604                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     58095604                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     58095604                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     58095604                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001222                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.001222                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005040                       # miss rate for WriteReq accesses
@@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                101560                       # number of replacements
-system.cpu.l2cache.tagsinuse             29278.940429                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             29278.942435                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  222505                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                132357                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  1.681097                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 24760.226438                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   3263.271337                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1255.442654                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 24760.228137                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   3263.271559                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1255.442739                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.755622                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.099587                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.038313                       # Average percentage of cache occupancy