Stats: Update stats for RAS and LRU fixes.

3 files changed, 208 insertions, 208 deletions

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 3ca0a8939..480848980 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index f3517e2c4..2acf8263c 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:59:31
+gem5 compiled Jun 28 2012 22:06:58
+gem5 started Jun 28 2012 22:58:54
 gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 202941992000 because target called exit()
+Exiting @ tick 202680458000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 3b1cc6fcd..b1d40b1a6 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.202942                       # Number of seconds simulated
-sim_ticks                                202941992000                       # Number of ticks simulated
-final_tick                               202941992000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.202680                       # Number of seconds simulated
+sim_ticks                                202680458000                       # Number of ticks simulated
+final_tick                               202680458000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1325068                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1342225                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2000847198                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231252                       # Number of bytes of host memory used
-host_seconds                                   101.43                       # Real time elapsed on the host
+host_inst_rate                                1918134                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1942970                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2892641209                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229316                       # Number of bytes of host memory used
+host_seconds                                    70.07                       # Real time elapsed on the host
 sim_insts                                   134398975                       # Number of instructions simulated
 sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            835264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8135040                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8970304                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       835264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          835264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5584960                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5584960                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13051                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             127110                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                140161                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           87265                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                87265                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              4115777                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             40085543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                44201320                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         4115777                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            4115777                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          27519982                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               27519982                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          27519982                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             4115777                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            40085543                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               71721303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            665664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7906112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8571776                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       665664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          665664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5301376                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5301376                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              10401                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             123533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                133934                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           82834                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                82834                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3284303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39007767                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                42292069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3284303                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3284303                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          26156325                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               26156325                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          26156325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3284303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39007767                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               68448395                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        405883984                       # number of cpu cycles simulated
+system.cpu.numCycles                        405360916                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   134398975                       # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs                      58160249                       # nu
 system.cpu.num_load_insts                    37275868                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  405883984                       # Number of busy cycles
+system.cpu.num_busy_cycles                  405360916                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                 184976                       # number of replacements
-system.cpu.icache.tagsinuse               2004.721102                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               2004.741762                       # Cycle average of tags in use
 system.cpu.icache.total_refs                134366560                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 718.445547                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           144544557000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    2004.721102                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.978868                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.978868                       # Average percentage of cache occupancy
+system.cpu.icache.warmup_cycle           144318639000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst    2004.741762                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.978878                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.978878                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    134366560                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       134366560                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     134366560                       # number of demand (read+write) hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst       187024                       # n
 system.cpu.icache.demand_misses::total         187024                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       187024                       # number of overall misses
 system.cpu.icache.overall_misses::total        187024                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   3166478000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   3166478000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   3166478000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   3166478000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   3166478000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3166478000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3055178000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3055178000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3055178000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3055178000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3055178000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3055178000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    134553584                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    134553584                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    134553584                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.001390
 system.cpu.icache.demand_miss_rate::total     0.001390                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001390                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001390                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16930.864488                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16930.864488                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16930.864488                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16335.753700                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16335.753700                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16335.753700                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16335.753700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16335.753700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16335.753700                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst       187024
 system.cpu.icache.demand_mshr_misses::total       187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst       187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total       187024                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2605406000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2605406000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2605406000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2605406000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2605406000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2605406000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2494106000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2494106000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2494106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2494106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2494106000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2494106000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001390                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13930.864488                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13930.864488                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13930.864488                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.753700                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.753700                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.753700                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.753700                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.753700                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.753700                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 146582                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.617150                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4087.606333                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              776708000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.617150                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997953                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997953                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    4087.606333                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997951                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997951                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     37185802                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        37185802                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
@@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data       150663                       # n
 system.cpu.dcache.demand_misses::total         150663                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       150663                       # number of overall misses
 system.cpu.dcache.overall_misses::total        150663                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1709246000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1709246000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5738404000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5738404000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data       462000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total       462000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7447650000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7447650000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7447650000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7447650000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1569302000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1569302000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5728156000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5728156000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       420000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       420000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7297458000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7297458000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7297458000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7297458000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     37231301                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     37231301                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
@@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_miss_rate::total     0.002593                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002593                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002593                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 37566.671795                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54566.239398                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        30800                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        30800                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 49432.508313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 49432.508313                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34490.911888                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34490.911888                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54468.791602                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54468.791602                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        28000                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total        28000                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 48435.634496                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 48435.634496                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 48435.634496                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 48435.634496                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       118818                       # number of writebacks
-system.cpu.dcache.writebacks::total            118818                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       122378                       # number of writebacks
+system.cpu.dcache.writebacks::total            122378                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        45499                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        45499                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       105164                       # number of WriteReq MSHR misses
@@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       150663
 system.cpu.dcache.demand_mshr_misses::total       150663                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       150663                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       150663                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1572749000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1572749000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5422912000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5422912000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       417000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total       417000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6995661000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6995661000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6995661000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6995661000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1432805000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1432805000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5412664000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5412664000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       375000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total       375000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6845469000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6845469000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6845469000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6845469000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005040                       # mshr miss rate for WriteReq accesses
@@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002593                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002593                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34566.671795                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51566.239398                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        27800                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        27800                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 46432.508313                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 46432.508313                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.911888                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31490.911888                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        25000                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        25000                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.634496                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.634496                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.634496                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.634496                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                120138                       # number of replacements
-system.cpu.l2cache.tagsinuse             19734.031622                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  212003                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                139002                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  1.525179                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                101560                       # number of replacements
+system.cpu.l2cache.tagsinuse             29288.840921                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  222505                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                132357                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.681097                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 15768.107062                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2612.732810                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1353.191750                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.481204                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.079734                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.041296                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.602235                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst       173973                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        19969                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         193942                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       118818                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       118818                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         3599                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         3599                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       173973                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        23568                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          197541                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       173973                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        23568                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         197541                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        13051                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        25530                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        38581                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       101580                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       101580                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        13051                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       127110                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        140161                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13051                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       127110                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       140161                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    678652000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1327560000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2006212000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5282160000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5282160000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    678652000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   6609720000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   7288372000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    678652000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   6609720000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   7288372000                       # number of overall miss cycles
+system.cpu.l2cache.occ_blocks::writebacks 24773.097821                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   3265.951230                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1249.791870                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.756015                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.099669                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.038141                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.893824                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst       176623                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        23301                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         199924                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       122378                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       122378                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         3844                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         3844                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       176623                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        27145                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          203768                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       176623                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        27145                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         203768                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        10401                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        22198                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32599                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       101335                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       101335                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        10401                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       123533                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        133934                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        10401                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       123533                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       133934                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    540852000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1154296000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1695148000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5269420000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5269420000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    540852000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   6423716000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   6964568000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    540852000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   6423716000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   6964568000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst       187024                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data        45499                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       232523                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       118818                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       118818                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       122378                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       122378                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       105179                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       105179                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst       187024                       # number of demand (read+write) accesses
@@ -316,17 +316,17 @@ system.cpu.l2cache.demand_accesses::total       337702                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst       187024                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       150678                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       337702                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.069782                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.561111                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.165923                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965782                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.965782                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.069782                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.843587                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.415043                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.069782                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.843587                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.415043                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.055613                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.487879                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.140197                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.963453                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.963453                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.055613                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.819848                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.396604                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.055613                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.819848                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.396604                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
@@ -346,41 +346,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        87265                       # number of writebacks
-system.cpu.l2cache.writebacks::total            87265                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13051                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        25530                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        38581                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101580                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       101580                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        13051                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       127110                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       140161                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        13051                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       127110                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       140161                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    522040000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1021200000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1543240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4063200000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4063200000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    522040000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5084400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5606440000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    522040000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5084400000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5606440000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.069782                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.561111                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.165923                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965782                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965782                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.069782                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.843587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.415043                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.069782                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.843587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.415043                       # mshr miss rate for overall accesses
+system.cpu.l2cache.writebacks::writebacks        82834                       # number of writebacks
+system.cpu.l2cache.writebacks::total            82834                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10401                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        22198                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32599                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101335                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       101335                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10401                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       123533                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       133934                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10401                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       123533                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       133934                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    416040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    887920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1303960000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4053400000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4053400000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    416040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4941320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5357360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    416040000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4941320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5357360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.055613                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.487879                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.140197                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.963453                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.963453                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.055613                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.819848                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.396604                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.055613                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.819848                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.396604                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency