diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/50.vortex/ref/sparc | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/50.vortex/ref/sparc')
6 files changed, 303 insertions, 203 deletions
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 2df6b792d..4295b5950 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -64,7 +77,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic +cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 542479326..7e99d8ae7 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:24:20 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:00:16 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index dc6c31998..12070ccfb 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.068149 # Nu sim_ticks 68148678500 # Number of ticks simulated final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3420916 # Simulator instruction rate (inst/s) -host_tick_rate 1712444497 # Simulator tick rate (ticks/s) -host_mem_usage 214012 # Number of bytes of host memory used -host_seconds 39.80 # Real time elapsed on the host -sim_insts 136139203 # Number of instructions simulated +host_inst_rate 3965699 # Simulator instruction rate (inst/s) +host_op_rate 4017046 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2010855033 # Simulator tick rate (ticks/s) +host_mem_usage 211680 # Number of bytes of host memory used +host_seconds 33.89 # Real time elapsed on the host +sim_insts 134398975 # Number of instructions simulated +sim_ops 136139203 # Number of ops (including micro ops) simulated system.physmem.bytes_read 685773693 # Number of bytes read from this memory system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory system.physmem.bytes_written 89882950 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 136297358 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.committedInsts 134398975 # Number of instructions committed +system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 5e34ae7a1..2507c0ed4 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -167,7 +159,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex bendian.raw -cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index 787eaa97a..a6a3d32b7 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 06:24:48 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 14:01:00 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 168a8eefa..b24bd2c93 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.202942 # Nu sim_ticks 202941992000 # Number of ticks simulated final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1608666 # Simulator instruction rate (inst/s) -host_tick_rate 2398029397 # Simulator tick rate (ticks/s) -host_mem_usage 222724 # Number of bytes of host memory used -host_seconds 84.63 # Real time elapsed on the host -sim_insts 136139203 # Number of instructions simulated +host_inst_rate 1927976 # Simulator instruction rate (inst/s) +host_op_rate 1952939 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2911235123 # Simulator tick rate (ticks/s) +host_mem_usage 220544 # Number of bytes of host memory used +host_seconds 69.71 # Real time elapsed on the host +sim_insts 134398975 # Number of instructions simulated +sim_ops 136139203 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8970304 # Number of bytes read from this memory system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory system.physmem.bytes_written 5584960 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 405883984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 136139203 # Number of instructions executed +system.cpu.committedInsts 134398975 # Number of instructions committed +system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 134366560 # To system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 2004.721102 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.978868 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits -system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits -system.cpu.icache.overall_hits 134366560 # number of overall hits -system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses -system.cpu.icache.overall_misses 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 3166478000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 3166478000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 3166478000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 16930.864488 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 16930.864488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 16930.864488 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 2004.721102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978868 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978868 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134366560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134366560 # number of overall hits +system.cpu.icache.overall_hits::total 134366560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses +system.cpu.icache.overall_misses::total 187024 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3166478000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3166478000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3166478000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3166478000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3166478000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3166478000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 134553584 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 2605406000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 2605406000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 2605406000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2605406000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2605406000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2605406000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2605406000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use @@ -102,38 +116,59 @@ system.cpu.dcache.total_refs 57960843 # To system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.617150 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997953 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 1709246000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5738404000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 462000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 7447650000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7447650000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 30800 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 49432.508313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 49432.508313 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4087.617150 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997953 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997953 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 57944942 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944942 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944942 # number of overall hits +system.cpu.dcache.overall_hits::total 57944942 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses +system.cpu.dcache.overall_misses::total 150663 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1709246000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1709246000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5738404000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5738404000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 462000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 462000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7447650000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7447650000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7447650000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7447650000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 58095605 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095605 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 118818 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1572749000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5422912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 417000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6995661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6995661000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34566.671795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51566.239398 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 27800 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 118818 # number of writebacks +system.cpu.dcache.writebacks::total 118818 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1572749000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1572749000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5422912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5422912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 417000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 417000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6995661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 120138 # number of replacements system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use @@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs 212003 # To system.cpu.l2cache.sampled_refs 139002 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.525179 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3965.924560 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15768.107062 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.121030 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.481204 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 193942 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 118818 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 3599 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 197541 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 197541 # number of overall hits -system.cpu.l2cache.ReadReq_misses 38581 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 101580 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 140161 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 140161 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 2006212000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 5282160000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 7288372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 7288372000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 118818 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165923 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.965782 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.415043 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.415043 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 15768.107062 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2612.732810 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1353.191750 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.481204 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.079734 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.041296 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.602235 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 173973 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 19969 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 193942 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 118818 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 118818 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3599 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3599 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 173973 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 23568 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 197541 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 173973 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 23568 # number of overall hits +system.cpu.l2cache.overall_hits::total 197541 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13051 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 25530 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 38581 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101580 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101580 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13051 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127110 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 140161 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13051 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 127110 # number of overall misses +system.cpu.l2cache.overall_misses::total 140161 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 678652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1327560000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2006212000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5282160000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5282160000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 678652000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6609720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7288372000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 678652000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6609720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7288372000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 118818 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 118818 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.069782 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.561111 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965782 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069782 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.843587 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069782 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.843587 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 87265 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 38581 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 101580 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 140161 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 140161 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1543240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4063200000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5606440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5606440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165923 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.965782 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.415043 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.415043 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 87265 # number of writebacks +system.cpu.l2cache.writebacks::total 87265 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13051 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 25530 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101580 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101580 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13051 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 127110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 140161 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13051 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 127110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 140161 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 522040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1021200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1543240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4063200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4063200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 522040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5084400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5606440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 522040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5084400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5606440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.561111 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965782 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |