stats: Bump stats for the fixes, and mostly DRAM controller changes

2 files changed, 80 insertions, 10 deletions

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index e0d531dce..56e5d21a1 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.068149                       # Nu
 sim_ticks                                 68148672000                       # Number of ticks simulated
 final_tick                                68148672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1921737                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1946620                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              974440461                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 287756                       # Number of bytes of host memory used
-host_seconds                                    69.94                       # Real time elapsed on the host
+host_inst_rate                                2339703                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2369997                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1186374997                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273296                       # Number of bytes of host memory used
+host_seconds                                    57.44                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -65,5 +65,40 @@ system.cpu.num_busy_cycles                  136297345                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu                  66342070     48.68%     57.07% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  325584      0.24%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::MemRead                 37296721     27.36%     84.68% # Class of executed instruction
+system.cpu.op_class::MemWrite                20884381     15.32%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  136293798                       # Class of executed instruction
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 43a817a48..736480ca6 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.202242                       # Nu
 sim_ticks                                202242260000                       # Number of ticks simulated
 final_tick                               202242260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 840358                       # Simulator instruction rate (inst/s)
-host_op_rate                                   851239                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1264562009                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296592                       # Number of bytes of host memory used
-host_seconds                                   159.93                       # Real time elapsed on the host
+host_inst_rate                                1069571                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1083420                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1609480248                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282012                       # Number of bytes of host memory used
+host_seconds                                   125.66                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -77,6 +77,41 @@ system.cpu.num_busy_cycles                  404484520                       # Nu
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
+system.cpu.op_class::No_OpClass              11445042      8.40%      8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu                  66342070     48.68%     57.07% # Class of executed instruction
+system.cpu.op_class::IntMult                        0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     57.07% # Class of executed instruction
+system.cpu.op_class::FloatAdd                  325584      0.24%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     57.31% # Class of executed instruction
+system.cpu.op_class::MemRead                 37296721     27.36%     84.68% # Class of executed instruction
+system.cpu.op_class::MemWrite                20884381     15.32%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
+system.cpu.op_class::total                  136293798                       # Class of executed instruction
 system.cpu.icache.tags.replacements            184976                       # number of replacements
 system.cpu.icache.tags.tagsinuse          2004.815325                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           134366547                       # Total number of references to valid blocks.