diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/long/se/50.vortex/ref/sparc | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/se/50.vortex/ref/sparc')
7 files changed, 115 insertions, 42 deletions
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 31ea2a719..49574e0d6 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr index bb51748c6..401e0da87 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall time(4026528248, 4026527848, ...) warn: ignoring syscall time(1375098, 4026527400, ...) diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 3e58ac7a5..ea448ddba 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:45:58 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:58:33 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 7d80c12bc..158c6976f 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.068149 # Nu sim_ticks 68148678500 # Number of ticks simulated final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1477309 # Simulator instruction rate (inst/s) -host_op_rate 1496437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 749087650 # Simulator tick rate (ticks/s) -host_mem_usage 221876 # Number of bytes of host memory used -host_seconds 90.98 # Real time elapsed on the host +host_inst_rate 2876458 # Simulator instruction rate (inst/s) +host_op_rate 2913702 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1458542737 # Simulator tick rate (ticks/s) +host_mem_usage 222372 # Number of bytes of host memory used +host_seconds 46.72 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 685773693 # Number of bytes read from this memory -system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory -system.physmem.bytes_written 89882950 # Number of bytes written to this memory -system.physmem.num_reads 171784884 # Number of read requests responded to by this memory -system.physmem.num_writes 20864304 # Number of write requests responded to by this memory -system.physmem.num_other 15916 # Number of other requests responded to by this memory -system.physmem.bw_read 10062905226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7897648844 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1318924328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11381829554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 538214332 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 147559361 # Number of bytes read from this memory +system.physmem.bytes_read::total 685773693 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214332 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214332 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory +system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 134553583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 37231301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784884 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory +system.physmem.num_other::total 15916 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7897648844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648844 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648844 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484180709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829554 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 136297358 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 29c16b40d..3ca0a8939 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index e764a6213..f3517e2c4 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:46:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:59:31 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 3a7d1778b..3b1cc6fcd 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.202942 # Nu sim_ticks 202941992000 # Number of ticks simulated final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 667455 # Simulator instruction rate (inst/s) -host_op_rate 676097 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1007854644 # Simulator tick rate (ticks/s) -host_mem_usage 230768 # Number of bytes of host memory used -host_seconds 201.36 # Real time elapsed on the host +host_inst_rate 1325068 # Simulator instruction rate (inst/s) +host_op_rate 1342225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2000847198 # Simulator tick rate (ticks/s) +host_mem_usage 231252 # Number of bytes of host memory used +host_seconds 101.43 # Real time elapsed on the host sim_insts 134398975 # Number of instructions simulated sim_ops 136139203 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8970304 # Number of bytes read from this memory -system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5584960 # Number of bytes written to this memory -system.physmem.num_reads 140161 # Number of read requests responded to by this memory -system.physmem.num_writes 87265 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 44201320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4115777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 27519982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 71721303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 835264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8135040 # Number of bytes read from this memory +system.physmem.bytes_read::total 8970304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 835264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 835264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5584960 # Number of bytes written to this memory +system.physmem.bytes_written::total 5584960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 127110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 140161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 87265 # Number of write requests responded to by this memory +system.physmem.num_writes::total 87265 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4115777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 40085543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 44201320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4115777 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4115777 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27519982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27519982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27519982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4115777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 40085543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 71721303 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 405883984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 134553584 # nu system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16930.864488 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16930.864488 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16930.864488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 2605406000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2605406000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 2605406000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13930.864488 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13930.864488 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 58095605 # nu system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37566.671795 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54566.239398 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 30800 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 30800 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49432.508313 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49432.508313 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6995661000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6995661000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6995661000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34566.671795 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51566.239398 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 27800 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 27800 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46432.508313 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 120138 # number of replacements system.cpu.l2cache.tagsinuse 19734.031622 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 150678 system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.069782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.561111 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165923 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965782 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965782 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069782 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.843587 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.415043 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069782 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.843587 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.415043 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5084400000 system.cpu.l2cache.overall_mshr_miss_latency::total 5606440000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.561111 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165923 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965782 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965782 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.415043 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.415043 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |